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| d a t a sh eet objective speci?cation file under integrated circuits, ic02 2000 jun 30 integrated circuits saa56xx enhanced tv microcontrollers with on-screen display (osd)
2000 jun 30 2 philips semiconductors objective speci?cation enhanced tv microcontrollers with on-screen display (osd) saa56xx contents 1 features 2 general description 3 quick reference data 4 ordering information 5 block diagram 6 pinning information 6.1 pinning 6.2 pin description 7 microcontroller 7.1 microcontroller features 8 memory organisation 8.1 rom bank switching 8.2 rom protection and verification 8.3 ram organisation 8.4 data memory 8.5 sfr memory 8.6 character set feature bits 8.7 movx memory 9 power-on reset 10 power saving modes of operation 10.1 standby mode 10.2 idle mode 10.3 power down mode 11 i/o facility 11.1 port type 12 interrupt system 12.1 interrupt enable structure 12.2 interrupt enable priority 12.3 interrupt vector address 12.4 level/edge interrupt 13 timers/counters 13.1 timer/counter 0 and timer/counter 1 13.2 timer/counter 2 14 watchdog timer 14.1 watchdog timer operation 15 port alternative functions 16 pulse width modulators 16.1 pwm control 16.2 tuning pulse width modulator (tpwm) 16.3 software adc (sad) 17 i 2 c-bus serial i/o 17.1 i 2 c-bus modes 17.2 i 2 c-bus port selection 18 uart peripheral 18.1 uart modes 18.2 uart multiprocessor communications 18.3 s0buf registers 18.4 uart baud rates 19 led support 20 external sram/rom interface 21 memory interface 21.1 memory structure 21.2 memory mapping 21.3 ccbase sfr 21.4 addressing memory 21.5 page clearing 21.6 multi-page operations 22 data capture 22.1 data capture features 23 display 23.1 display features 23.2 display modes 23.3 display timing modes 23.4 display feature descriptions 23.5 character and attribute coding 23.6 screen and global controls 23.7 screen colour 23.8 text display controls 23.9 soft scroll action 23.10 display positioning 23.11 character set 23.12 rgb brightness control 24 memory mapped registers (mmrs) 25 in-system programming interface 26 limiting values 27 characteristics 28 quality and reliability 29 application information 29.1 application diagram 29.2 external sram implementation 30 emc guidelines 31 package outline 32 soldering 33 data sheet status 34 definitions 35 disclaimers 36 purchase of philips i 2 c components 2000 jun 30 3 philips semiconductors objective speci?cation enhanced tv microcontrollers with on-screen display (osd) saa56xx 1 features single-chip higher frequency microcontroller with integrated on-screen display (osd) versions available with integrated data capture both active high and active low reset pins otp memory for both program rom and character sets in-system programming (isp) option for the embedded otp memories using ieee1149 (jtag: joint test action group) interface single power supply: 3.0 to 3.6 v 5 v tolerant digital inputs and i/o 32 i/o ports via individual addressable controls larger character rom, up to 1020 characters of 12 10 pixels smoothing capability on sized characters programmable i/o for push-pull, open-drain and quasi-bidirectional and high impedance two port lines with 8 ma sink (at <0.4 v) capability, for direct drive of led single crystal oscillator for microcontroller, osd and data capture power reduction modes: idle, standby and power-down byte level i 2 c-bus up to 400 khz dual port i/o 64 dynamically redefinable characters for osds increased special graphic characters allowing four colours per character selectable character height 9, 10, 13 and 16 tv lines pin compatibility throughout family operating temperature: - 20 to +70 c. 2 general description the saa56xx family of microcontrollers are a derivative of the philips industry-standard 80c51 microcontroller and are intended for use as the central control mechanism in a television receiver. they provide control functions for the television system, osd and incorporate an integrated data capture and display function for either teletext or closed caption. additional features over the saa55xx family have been included, e.g. 100/120 hz (2h/2v only) display timing modes, two page operation (50 hz mode only for 16:9), higher frequency microcontroller, increased character storage, more 80c51 peripherals and a larger display memory. as with the rest of the saa55xx family, the data capture hardware can decode and display both 525 line and 625 line world system teletext (wst), closed caption information, video programming system (vps) information and wide screen signalling (wss) information. the same display hardware is used for teletext, closed caption and on-screen display, which means that the display features available give greater flexibility to differentiate the tv set. the family of devices offers a range of memory variants with program rom sizes of 128-kbyte and 192-kbyte, also up to 14 kbytes of ram. 2000 jun 30 4 philips semiconductors objective speci?cation enhanced tv microcontrollers with on-screen display (osd) saa56xx 3 quick reference data 4 ordering information notes 1. nnnn is a four digit number uniquely referencing the microcontroller program mask. 2. extendible to 8-kbyte in external sram application, see figure 8 3. text only full feature device. symbol parameter min. typ. max. unit supply v ddx any supply voltage (v dd to v ss ) 3.0 3.3 3.6 v i ddp periphery supply current 1.0 -- ma i ddc core supply current - 15.0 18.0 ma i dd(id) idle mode supply current - 4.6 6.0 ma i dd(pd) power-down mode supply current - 0.76 1.0 ma i dda analog supply current - 45.0 48.0 ma i dda(id) idle mode analog supply current - 0.87 1.0 ma i dda(pd) power-down mode analog supply current - 0.45 0.7 ma f xtal crystal frequency - 12.0 - mhz t amb operating ambient temperature - 20 - +70 c t stg storage temperature - 55 - +125 c type number (1) package rom data ram text pages name description version saa5667hl/nnnn lqfp100 plastic low pro?le quad ?at package; 100 leads; body 14 14 1.4 mm sot407-1 192-kbyte 2-kbyte (2) 12 (3) saa5647hl/nnnn 192-kbyte cc-osd only SAA5645HL/nnnn 128-kbyte cc-osd only 2000 jun 30 5 philips semiconductors objective speci?cation enhanced tv microcontrollers with on-screen display (osd) saa56xx 5 block diagram handbook, full pagewidth gsa023 microprocessor (80c51) sram 256-byte rom (128 or 192-kbyte) memory interface display r g b vds hsync vsync cvbs data capture dram (14-kbyte) tv control and interface i 2 c-bus, general i/o display timing cvbs data capture timing fig.1 block diagram (top level architure). 2000 jun 30 6 philips semiconductors objective speci?cation enhanced tv microcontrollers with on-screen display (osd) saa56xx 6 pinning information 6.1 pinning handbook, full pagewidth 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 p3.7 p0.4/int4 a6 p0.3/int3 vpe ale psen p0.2/int2 p0.1/tx p0.0/rx a7 ea p0.5 v ssp v ssc wr rd a14 a15_ln p3.3/adc3 p3.2/adc2 p3.1/adc1 a17_ln p3.0/adc0 p2.7/pwm6 rambk0 vds hsync p3.5/int5 vsync rombk2 rombk1 rombk0 p3.6 v ssp intd v ssc v ddc a11 a10 a9 a8 movx_wr oscgnd xtalin xtalout reset reset movx_rd v ddp 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 p2.0/tpwm v ssc p2.6/pwm5 p2.5/pwm4 p2.4/pwm3 p2.3/pwm2 p2.2/pwm1 p2.1/pwm0 ad7 ad6 ad5 ad4 ad3 ad2 ad1 ad0 p1.5/sda1 p1.4/scl1 p1.7/sda0 p1.6/scl0 p1.3/t1 p1.2/int0 p1.1/t0 a16_ln p1.0/int1 a5 a4 p0.6 p0.7/t2 v ssa cvbs0 cvbs1 a15_bk sync_filter iref a13 a12 a3 a2 a1 frame vpe cor p3.4/pwm7/t2ex v dda b g r a0 rambk1 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 gsa020 saa56xx fig.2 pin configuration. 2000 jun 30 7 philips semiconductors objective speci?cation enhanced tv microcontrollers with on-screen display (osd) saa56xx 6.2 pin description table 1 lqfp100 package symbol pin type description p2.0/tpwm 100 i/o port 2. 8-bit programmable bidirectional port with alternative functions. p2.0/tpwm is the output for the 14-bit high precision pwm; p2.1/pwm0 to p2.7/pwm6 are the outputs for the 6-bit pwms 0 to 6. p2.1/pwm0 93 i/o p2.2/pwm1 94 i/o p2.3/pwm2 95 i/o p2.4/pwm3 96 i/o p2.5/pwm4 97 i/o p2.6/pwm5 98 i/o p2.7/pwm6 1 i/o p3.0/adc0 2 i/o port 3. 8-bit programmable bidirectional port with alternative functions. p3.0/adc0 to p3.3/adc3 are the inputs for the software adc facility and p3.4/pwm7 is the output for the 6-bit pwm7; p3.4/pwm7/t2ex is the output for the 6-bit pwm7 or the timer 2 control; p3.5/int5 is the external interrupt 5; p3.6 and p3.7 have no alternative functions. p3.1/adc1 4 i/o p3.2/adc2 5 i/o p3.3/adc3 6 i/o p3.4/pwm7/t2ex 44 i/o p3.5/int5 54 i/o p3.6 59 i/o p3.7 25 i/o v ssc 11, 62, 99 - core ground p0.0/rx 16 i/o port 0. 8-bit programmable bidirectional port (with alternative functions). p0.0/rx and p0.1/tx are respectively the serial transmit and receive for the uart; p0.2/int2 to p0.4/int4 are the external interrupts 2 to 4; p0.5 and p0.6 have no alternative functions and have 8 ma current sinking capability for direct drive of leds. p0.1/tx 17 i/o p0.2/int2 18 i/o p0.3/int3 22 i/o p0.4/int4 24 i/o p0.5 13 i/o p0.6 28 i/o p0.7/t2 29 i/o v ssa 30 - analog ground cvbs0 31 i 2 composite video input selectable via sfr; a positive-going 1 v (peak-to-peak) input is required, connected via a 100 nf capacitor cvbs1 32 i sync_filter 34 i/o cvbs sync ?lter input; this pin should be connected to v ssa via a 100 nf capacitor. iref 35 i reference current input for analog circuits, connected to v ssa via a 24 k w resistor. frame 41 o de-interlace output synchronized with the vsync pulse to produce a non-interlaced display by adjustment of the vertical de?ection circuits. vpe 21, 42 i otp programming voltage cor 43 o open-drain, active low output which allows selective contrast reduction of the tv picture to enhance a mixed mode display. v dda 45 - +3.3 v analog power supply b 46 o pixel rate output of the blue colour information 2000 jun 30 8 philips semiconductors objective speci?cation enhanced tv microcontrollers with on-screen display (osd) saa56xx g 47 o pixel rate output of the green colour information r 48 o pixel rate output of the red colour information vds 52 o video/data switch push-pull output for dot rate fast blanking hsync 53 i schmitt triggered input for a ttl-level version of the horizontal sync pulse; the polarity of this pulse is programmable by register bit txt1.h polarity. vsync 55 i schmitt triggered input for a ttl-level version of the vertical sync pulse; the polarity of this pulse is programmable by register bit txt1.v polarity. v ssp 12, 60 - periphery ground v ddc 63 - +3.3 v core power supply oscgnd 69 - crystal oscillator ground xtalin 70 i 12 mhz crystal oscillator input xtalout 71 o 12 mhz crystal oscillator output reset 72 i if the reset input is low for at least 24 crystal oscillator periods while the oscillator is running, the device is reset (internal pull-up). reset 73 i if the reset input is high for at least 24 crystal oscillator periods while the oscillator is running, the device is reset. this pin should be connected to v ddc via a capacitor if an active high reset is required (internal pull-down). v ddp 75 - +3.3 v periphery power supply p1.0/int1 76 i/o port 1. 8-bit programmable bidirectional port with alternative functions. p1.0/int1 is external interrupt 1 which can be triggered on the rising and falling edge of the pulse; p1.1/t0 is timer/counter 0; p1.2/int0 is external interrupt 0; p1.3/t1 is timer/counter 1; p1.6/scl0 is the serial clock input for the i 2 c-bus; p1.7/sda0 is the serial data port for the i 2 c-bus; p1.4/scl1 is the serial clock input for the i 2 c-bus; p1.5/sda1 is the serial data port for the i 2 c-bus. p1.1/t0 78 i/o p1.2/int0 79 i/o p1.3/t1 80 i/o p1.6/scl0 81 i/o p1.7/sda0 82 i/o p1.4/scl1 83 i/o p1.5/sda1 84 i/o rd 9 o read control signal to external data memory wr 10 o write control signal to external data memory ea 14 i control signal used to select external (low) or internal (high) program memory (internal pull-up) psen 19 o enable signal for external program memory ale 20 o external latch enable signal; active high ad0 to ad7 85 to 92 i/o address lines a0 to a7 multiplexed with data lines d0 to d7. a0 to a7 49, 40, 39, 38, 27, 26, 23, 15 o address lines a0 to a7 a8 to a14 67 to 64, 37, 36, 8 o address lines a8 to a14 a15_ln to a17_ln 7, 77, 3 o address lines a15 to a17; note 1 movx_wr 68 o movx write for hitex 80c51 emulation (internal movx write instruction) movx_rd 74 o movx read for hitex 80c51 emulation (internal movx read instruction) a15_bk 33 o address line a15 when using rombk outputs for external program rom access symbol pin type description 2000 jun 30 9 philips semiconductors objective speci?cation enhanced tv microcontrollers with on-screen display (osd) saa56xx note 1. a15_ln, a16_ln and a17_ln form a linear address space and may be used as an alternative to a15_bk (pin 33) and rombk2 to rombk0 (pins 56, 57 and 58) for external program rom access. 7 microcontroller the functionality of the microcontroller used on this device is described here with reference to the industry standard 80c51 microcontroller. a full description of its functionality can be found in handbook ic20 80c51-based 8-bit microcontrollers . 7.1 microcontroller features 80c51 microcontroller core standard instruction set and timing 1 m s/0.5 m s machine cycle maximum 192k 8-bit program rom maximum of 14k 8-bit data and display ram 15 level interrupt controller with individual enable/disable and two level priority up to six external interrupts with programmable detection characteristics three 16-bit timer/counter registers watchdog timer auxiliary ram page pointer 16-bit data pointer idle, standby and power-down modes 32 general i/o lines eight 6-bit pulse width modulator (pwm) outputs for control of tv analog signals one 14-bit pwm for voltage synthesis tuner (vst) control 8-bit analog-to-digital converter (adc) with four multiplexed inputs two high current outputs for directly driving leds etc. i 2 c-bus byte level interface with dual ports uart for asynchronous serial communication external rom and sram compatibility. rombk0 to rombk2 58 to 56 o rombk sfr selection bits for external program rom access >64 kbytes rambk0 to rambk1 51, 50 o rombk sfr selection bits for external program sram data storage >64 kbytes. use a0 to a14 and a15_bk as lower address bits intd 61 i interrupt disable for emulation (internal pull-up) symbol pin type description 2000 jun 30 10 philips semiconductors objective speci?cation enhanced tv microcontrollers with on-screen display (osd) saa56xx 8 memory organisation the device has the capability of a maximum of 192-kbyte program rom and 14-kbyte data ram internally. 8.1 rom bank switching the 128-kbyte program rom variant is arranged in four banks of 32 kbytes. one of the 32-kbyte banks is common and is always addressable. the other three banks (bank 0, bank 1 and bank 2) can be selected with sfr rombk bits <2:0> (see table 2 and fig. 3). the 192-kbyte program rom variant is arranged in six banks of 32 kbytes. one of the 32-kbyte banks is common and is always addressable. the other five banks (bank 0, bank 1, bank 2, bank 3 and bank 4) can be selected with sfr rombk bits <2:0> (see table 2 and fig. 3). table 2 rom bank selection rombk2 rombk1 rombk0 0to 32-kbyte 32 to 64-kbyte 0 0 0 common bank 0 0 0 1 common bank 1 0 1 0 common bank 2 0 1 1 common bank 3 1 0 0 common bank 4 1 0 1 reserved reserved 1 1 0 reserved reserved 1 1 1 reserved reserved handbook, full pagewidth gsa073 7fffh 0000h common (32-kbyte) physical address range: 0 to 32-kbyte ffffh 8000h bank 2 (32-kbyte) ffffh 8000h bank 3 (32-kbyte) ffffh 8000h bank 4 (32-kbyte) ffffh 8000h bank 1 (32-kbyte) ffffh 8000h bank 0 (32-kbyte) physical address range: 96 to 128-kbyte physical address range: 128 to 160-kbyte physical address range: 160 to 192-kbyte physical address range: 64 to 96-kbyte physical address range: 32 to 64-kbyte fig.3 internal program memory. 2000 jun 30 11 philips semiconductors objective speci?cation enhanced tv microcontrollers with on-screen display (osd) saa56xx 8.2 rom protection and veri?cation saa56xx devices have a set of security bits allied with each section of the device, i.e. program rom, character rom and packet 26 rom. the security bits are used to prevent the rom from being overwritten once programmed, and also the contents being verified once programmed. the security bits can be programmed once only and cannot be erased. the saa56xx security bits are set as shown in fig.4 for production programmed devices and are set as shown in fig.5 for production blank devices. handbook, full pagewidth gsa036 program rom (128 or 192 kbytes) memory user rom programming verify disabled enabled disabled enabled disabled enabled security bits set character rom (12 kbytes) packet 26 rom (4 kbytes) fig.4 security bits for production programmed devices. handbook, full pagewidth gsa037 program rom (128 or 192 kbytes) memory user rom programming verify enabled enabled enabled enabled enabled enabled security bits set character rom (12 kbytes) packet 26 rom (4 kbytes) fig.5 security bits for production blank devices. 2000 jun 30 12 philips semiconductors objective speci?cation enhanced tv microcontrollers with on-screen display (osd) saa56xx 8.3 ram organisation fig.6 shows the internal data ram is organised into two areas, data memory and special function registers (sfrs). 8.4 data memory the data memory (see fig.6) is 256 8 bits and occupies address range 00h to ffh when using indirect addressing and 00h to 7fh when using direct addressing. the sfrs occupy the address range 80h to ffh and are accessible using direct addressing only. the lower 128 bytes of data memory are mapped as shown in fig.7. the lowest 32 bytes are grouped into four banks of eight registers selectable via sfr psw bits <4:3> (rs1/rs0 - see table 3), the next 16 bytes above the register banks form a block of bit addressable memory space. the upper 128 bytes are not allocated for any special area or functions. table 3 bank selection rs1 rs0 bank 0 0 bank 0 0 1 bank 1 1 0 bank 2 1 1 bank 3 handbook, halfpage mbk956 accessible by indirect addressing only data memory ffh upper 128 bytes lower 128 bytes 80h 7fh 00h special function registers accessible by direct and indirect addressing accessible by direct addressing only fig.6 internal data memory. handbook, halfpage gsa060 07h 00h 0fh 08h 17h 10h 1fh 18h 2fh 7fh 20h bit-addressable space (bit addresses 00h to 7fh) 4 banks of 8 registers (r0 to r7) bank select bits in psw 11 = bank 3 01 = bank 1 00 = bank 0 10 = bank 2 fig.7 lower 128 bytes of internal ram. 2000 jun 30 13 philips semiconductors objective speci?cation enhanced tv microcontrollers with on-screen display (osd) saa56xx this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... 8.5 sfr memory the special function register (sfr) space is used for port latches, timer, peripheral control, acquisition control and display control, etc. these r egisters can only be accessed by direct addressing. sixteen of the addresses in the sfr space are both bit and byte addressable. the bit addressable sfrs are those whose address ends in 0h or 8h. table 4 only presents the additional sfrs of the saa56xx family over the saa55xx family of devices. this sfr map table must therefore be read in conjunction with the saa55xx sfr map table. a description of the new sfr bits is shown in table 5, which presents the sfrs in alphabetical order. table 4 sfr memory map add r/w name 7 6 5 4 3 2 1 0 reset 80h r/w p0 p07 p06 p05 p04 p03 p02 p01 p00 ffh 81h r/w sp sp7 sp6 sp5 sp4 sp3 sp2 sp1 sp0 07h 82h r/w dpl dpl7 dpl6 dpl5 dpl4 dpl3 dpl2 dpl1 dpl0 00h 83h r/w dph dph7 dph6 dph5 dph4 dph3 dph2 dph1 dph0 00h 84h r/w ien1 ex5 ex4 ex3 ex2 eutx eurx euart et2 00h 85h r/w ip1 px5 px4 px3 px2 putx purx puart pt2 00h 86h r/w extint ex5cfg1 ex5cfg0 ex4cfg1 ex4cfg0 ex3cfg1 ex3cfg0 ex2cfg1 ex2cfg0 00h 87h r/w pcon smod ard rfi wle gf1 gf0 pd idl 00h 88h r/w tcon tf1 tr1 tf0 tr0 ie1 it1 ie0 it0 00h 89h r/w tmod gate c/ tm1 m0 gatec/ tm1m000h 8ah r/w tl0 tl07 tl06 tl05 tl04 tl03 tl02 tl01 tl00 00h 8bh r/w tl1 tl17 tl16 tl15 tl14 tl13 tl12 tl11 tl10 00h 8ch r/w th0 th07 th06 th05 th04 th03 th02 th01 th00 00h 8dh r/w th1 th17 th16 th15 th14 th13 th12 th11 th10 00h 90h r/w p1 p17 p16 p15 p14 p13 p12 p11 p10 ffh 91h r/w gpr1 gpr17 gpr16 gpr15 gpr14 gpr13 gpr12 gpr11 gpr10 00h 92h r/w gpr2 gpr27 gpr26 gpr25 gpr24 gpr23 gpr22 gpr21 gpr20 00h 93h r/w gpr3 gpr37 gpr36 gpr35 gpr34 gpr33 gpr32 gpr31 gpr30 00h 94h r/w gpr4 gpr47 gpr46 gpr45 gpr44 gpr43 gpr42 gpr41 gpr40 00h 95h r/w gpr5 gpr57 gpr56 gpr55 gpr54 gpr53 gpr52 gpr51 gpr50 00h 96h r/w p0cfga p0cfga7 p0cfga6 p0cfga5 p0cfga4 p0cfga3 p0cfga2 p0cfga1 p0cfga0 ffh 97h r/w p0cfgb p0cfgb7 p0cfgb6 p0cfgb5 p0cfgb4 p0cfgb3 p0cfgb2 p0cfgb1 p0cfgb0 00h 98h r/w sadb 0 0 0 dc_comp sad3 sad2 sad1 sad0 00h 99h r/w s0con sm0 sm1 sm2 ren tb8 rb8 ti ri 00h 9ah r/w s0buf s0buf s0buf6 s0buf5 s0buf4 s0buf3 s0buf2 s0buf1 s0buf0 00h 2000 jun 30 14 philips semiconductors objective speci?cation enhanced tv microcontrollers with on-screen display (osd) saa56xx this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... 9ch r/w gpr6 gpr67 gpr66 gpr65 gpr64 gpr63 gpr62 gpr61 gpr60 00h 9dh r/w gpr7 gpr77 gpr76 gpr75 gpr74 gpr73 gpr72 gpr71 gpr70 00h 9eh r/w p1cfga p1cfga7 p1cfga6 p1cfga5 p1cfga4 p1cfga3 p1cfga2 p1cfga1 p1cfga0 ffh 9fh r/w p1cfgb p1cfgb7 p1cfgb6 p1cfgb5 p1cfgb4 p1cfgb3 p1cfgb2 p1cfgb1 p1cfgb0 00h a0h r/w p2 p27 p26 p25 p24 p23 p22 p21 p20 ffh a1h r txt31 ---- gpf11 gpf10 gpf9 gpf8 00h a2h r txt32 9fe11 9ff11 9ff10 9ff9 9ff8 9ff7 9ff6 9ff5 00h a3h r txt33 bfe7 bfe6 bfe5 bfe4 bfe3 bfe2 bfe1 bfe0 00h a4h r txt34 ---- bfe11 bfe10 bfe9 bfe8 00h a5h r/w gpr8 gpr87 gpr86 gpr85 gpr84 gpr83 gpr82 gpr81 gpr80 00h a6h r/w p2cfga p2cfga7 p2cfga6 p2cfga5 p2cfga4 p2cfga3 p2cfga2 p2cfga1 p2cfga0 ffh a7h r/w p2cfgb p2cfgb7 p2cfgb6 p2cfgb5 p2cfgb4 p2cfgb3 p2cfgb2 p2cfgb1 p2cfgb0 00h a8h r/w ie ea ebusy es2 ecc et1 ex1 et0 ex0 00h a9h r/w txt23 not b 3 not b 2 not b 1 not b 0 east/ west b drcs b enable bs b1 bs b0 00h aah r/w txt24 bkgnd out b bkgnd in b corb out b corb in b text out b text in b picture on out b picture on in b 00h abh r/w txt25 bkgnd out b bkgnd in b corb out b corb in b text out b text in b picture on out b picture on in b 00h ach r/w txt26 extended drcs trans b c mesh enable b b mesh enable b shadow enable b box on 24 b box on 1 b to 23 b box on 0 b 00h adh r/w txt28 multi page cc_txt b active pag e display bank b page b3 page b2 page b1 page b0 00h b0h r/w p3 1 1 1 p34 p33 p32 p31 p30 ffh b1h r/w txt27 ---- scrb2 scrb1 scrb0 00h b2h r/w txt18 not3 not2 not1 not0 0 0 bs1 bs0 00h b3h r/w txt19 ten tc2 tc1 tc0 0 0 ts1 ts0 00h b4h r/w txt20 drcs enable osd planes extended special graphics char select enable osd lang enable osd lan2 osd lan1 osd lan0 00h b5h r/w txt21 disp lines1 disp lines0 char size1 char size0 i 2 c port 1 cc on i 2 c port 0 cc/txt 02h b6h r txt22 gpf7 gpf6 gpf5 gpf4 gpf3 gpf2 gpf1 gpfo xxh add r/w name 7 6 5 4 3 2 1 0 reset 2000 jun 30 15 philips semiconductors objective speci?cation enhanced tv microcontrollers with on-screen display (osd) saa56xx this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... b7h r/w cclin 0 0 0 cs4 cs3 cs2 cs1 cs0 15h b8h r/w ip 0 pbusy pes2 pcc pt1 px1 pt0 px0 00h b9h r/w txt17 0 force acq1 force acq0 force disp1 force disp0 screen col2 screen col1 screen col0 00h bah r wss1 0 0 0 wss<3:0> error wss3 wss2 wss1 wss0 00h bbh r wss2 0 0 0 wss<7:4> error wss7 wss6 wss5 wss4 00h bch r wss3 wss<13:11> error wss13 wss12 wss11 wss<10:8> error wss10 wss9 wss8 00h bdh r/w gpr9 gpr97 gpr96 gpr95 gpr94 gpr93 gpr92 gpr91 gpr90 00h beh r/w p3cfga p3cfga7 p3cfga6 p3cfga5 p3cfga4 p3cfga3 p3cfga2 p3cfga1 p3cfga0 ffh bfh r/w p3cfgb p3cfgb7 p3cfgb6 p3cfgb5 p3cfgb4 p3cfgb3 p3cfgb2 p3cfgb1 p3cfgb0 00h c0h r/w txt0 x24 posn display x24 auto frame disable header roll display status row only disable frame vps on inv on 00h c1h r/w txt1 ext pkt off 8-bit acq off x26 off full field field polarity h polarity v polarity 00h c2h r/w txt2 acq bank req3 req2 req1 req0 sc2 sc1 sc0 00h c3h w txt3 --- prd4 prd3 prd2 prd1 prd0 00h c4h r/w txt4 osd bank enable quad width enable east/ west disable double height b mesh enable c mesh enable trans enable shadow enable 00h c5h r/w txt5 bkgnd out bkgnd in cor out cor in text out text in picture on out picture on in 03h c6h r/w txt6 bkgnd out bkgnd in cor out cor in text out text in picture on out picture on in 03h c7h r/w txt7 status row top cursor on reveal bottom/ t op double height box on 24 box on 1-23 box on 0 00h c8h r/w txt8 (reserved) 0 flicker st op on (reserved) 0 disable spanish pkt 26 received wss received wss on cvbs1/ cvbs0 00h c9h r/w txt9 cursor freeze clear memory a0 r4 r3 r2 r1 r0 00h cah r/w txt10 0 0 c5 c4 c3 c2 c1 c0 00h cbh r/w txt11 d7 d6 d5 d4 d3 d2 d1 d0 00h add r/w name 7 6 5 4 3 2 1 0 reset 2000 jun 30 16 philips semiconductors objective speci?cation enhanced tv microcontrollers with on-screen display (osd) saa56xx this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... cch r txt12 525/ 625 sync spanish rom ver3 rom ver2 rom ver1 rom ver0 1 video signal quality xxxx xx1x cdh r/w txt14 0 0 0 display bank page3 page2 page1 page0 00h ceh r/w txt15 0 0 0 micro bank block3 block2 block1 block0 00h cfh r/w ccbase ccbase7 ccbase6 ccbase5 ccbase4 ccbase3 ccbase2 ccbase1 ccbase0 20h d0h r/w psw c ac f0 rs1 rs0 ov - p 00h d1h r/w gpr10 gpr107 gpr106 gpr105 gpr104 gpr103 gpr102 gpr101 gpr100 00h d2h r/w tdacl td7 td6 td5 td4 td3 td2 td1 td0 00h d3h r/w tdach tpwe 1 td13 td12 td11 td10 td9 td8 40h d4h r/w pwm7 pw7e 1 pw7v5 pw7v4 pw7v3 pw7v2 pw7v1 pw7v0 40h d5h r/w pwm0 pw0e 1 pw0v5 pw0v4 pw0v3 pw0v2 pw0v1 pw0v0 40h d6h r/w pwm1 pw1e 1 pw1v5 pw1v4 pw1v3 pw1v2 pw1v1 pw1v0 40h d7h r ccdat1 ccd17 ccd16 ccd15 ccd14 ccd13 ccd12 ccd11 ccd10 00h d8h r/w s1con cr2 ensi sta sto si aa cr1 cr0 00h d9h r s1sta stat4 stat3 stat2 stat1 stat0 0 0 0 f8h dah r/w s1dat dat7 dat6 dat5 dat4 dat3 dat2 dat1 dat0 00h dbh r/w s1adr adr6 adr5 adr4 adr3 adr2 adr1 adr0 gc 00h dch r/w pwm3 pw3e 1 pw3v5 pw3v4 pw3v3 pw3v2 pw3v1 pw3v0 40h ddh r/w pwm4 pw4e 1 pw4v5 pw4v4 pw4v3 pw4v2 pw4v1 pw4v0 40h deh r/w pwm5 pw5e 1 pw5v5 pw5v4 pw5v3 pw5v2 pw5v1 pw5v0 40h dfh r/w pwm6 pw6e 1 pw6v5 pw6v4 pw6v3 pw6v2 pw6v1 pw6v0 40h e0h r/w acc acc7 acc6 acc5 acc4 acc3 acc2 acc1 acc0 00h e1h r/w txt29 ten b ts b1 ts b0 osd planes b osd lang enable b osd lan b2 osd lan b1 osd lan b0 00h e2h r/w txt30 tc b2 tc b1 tc b0 reserved reserved reserved reserved reserved 00h e3h r/w gpr11 gpr117 gpr116 gpr115 gpr114 gpr113 gpr112 gpr111 gpr110 00h e4h r/w pwm2 pw2e 1 pw2v5 pw2v4 pw2v3 pw2v2 pw2v1 pw2v0 40h e5h r/w gpr12 gpr127 gpr126 gpr125 gpr124 gpr123 gpr122 gpr121 gpr120 00h e6h r/w gpr13 gpr137 gpr136 gpr135 gpr134 gpr133 gpr132 gpr131 gpr130 00h e7h r ccdat2 ccd27 ccd26 ccd25 ccd24 ccd23 ccd22 ccd21 ccd20 00h add r/w name 7 6 5 4 3 2 1 0 reset 2000 jun 30 17 philips semiconductors objective speci?cation enhanced tv microcontrollers with on-screen display (osd) saa56xx this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... e8h r/w sad vhi ch1 ch0 st sad7 sad6 sad5 sad4 00h e9h r/w gpr14 gpr147 gpr146 gpr145 gpr144 gpr143 gpr142 gpr141 gpr140 00h eah r/w gpr15 gpr157 gpr156 gpr155 gpr154 gpr153 gpr152 gpr151 gpr150 00h ebh r/w gpr16 gpr167 gpr166 gpr165 gpr164 gpr163 gpr162 gpr161 gpr160 00h ech r/w gpr17 gpr177 gpr176 gpr175 gpr174 gpr173 gpr172 gpr171 gpr170 00h edh r/w gpr18 gpr187 gpr186 gpr185 gpr184 gpr183 gpr182 gpr181 gpr180 00h eeh r/w txt35 pkt1-247 pkt1-246 pkt1-245 pkt1-244 pkt1-243 pkt1-242 pkt1-241 pkt1-240 00h efh r/w txt36 ------ pkt1-249 pkt1-248 00h f0h r/w b b7 b6 b5 b4 b3 b2 b1 b0 00h f1h r/w t2con tf2 exf2 rclk0 tclk0 exen2 tr2 c/t2 cp/rl2 00h f2h r/w t2mod -- rclk1 tclk1 - t2rd t2oe dcen 00h f3h r/w rcap2l rcap2l7 rcap2l6 rcap2l5 rcap2l4 rcap2l3 rcap2l2 rcap2l1 rcap2l0 00h f4h r/w rcap2h rcap2h7 rcap2h6 rcap2h5 rcap2h4 rcap2h3 rcap2h2 rcap2h1 rcap2h0 00h f5h r/w tl2 tl27 tl26 tl25 tl24 tl23 tl22 tl21 tl20 00h f6h r/w th2 th27 th26 th25 th24 th23 th22 th1 th20 00h f8h r/w txt13 vps received pag e clearing 525 display 525 text 625 text pkt 8/30 fastext 0 xxxx xxx0 f9h r/w gpr19 gpr197 gpr196 gpr195 gpr194 gpr193 gpr192 gpr191 gpr190 00h fah r/w xramp xramp7 xramp6 xramp5 xramp4 xramp3 xramp2 xramp1 xramp0 00h fb r/w rombk standby iic_lut1 iic_lut0 rambk1 rambk0 rombk2 rombk1 rombk0 00h fch r/w gpr20 gpr207 gpr206 gpr205 gpr204 gpr203 gpr202 gpr201 gpr200 00h fdh r test test7 test6 test5 test4 test3 test2 test1 test0 00h feh w wdtkey wkey7 wkey6 wkey5 wkey4 wkey3 wkey2 wkey1 wkey0 00h ffh r/w wdt wdv7 wdv6 wdv5 wdv4 wdv3 wdv2 wdv1 wdv0 00h add r/w name 7 6 5 4 3 2 1 0 reset 2000 jun 30 18 philips semiconductors objective speci?cation enhanced tv microcontrollers with on-screen display (osd) saa56xx table 5 sfr bit description bits function accumulator (acc) acc7 to acc0 accumulator value b register (b) b7 to b0 b register value cc base pointer (ccbase) ccbase7 to ccbase0 closed caption display base pointer cc data byte 1 (ccdat1) ccd17 to ccd10 closed caption ?rst data byte cc data byte 2 (ccdat2) ccd26 to ccd20 closed caption second data byte cc line (cclin) cs4 to cs0 closed caption slice line using 525-line number data pointer high byte (dph) dph7 to dph0 data pointer high byte, used with dpl to address auxiliary memory data pointer low byte (dpl) dpl7 to dpl0 data pointer low byte, used with dph to address auxiliary memory external interrupt (extint) (n = 2 to 5) exncfg<1:0> = 00 active low interrupt exncfg<1:0> = 01 rising edge interrupt exncfg<1:0> = 10 falling edge interrupt exncfg<1:0> = 11 both rising and falling edge interrupt general purpose registers (gpr1 to gpr20) (n = 1 to 21) gprn<7:0> general purpose read/write registers available for use by the embedded software interrupt enable register (ie) ea disable all interrupts (logic 0), or use individual interrupt enable bits (logic 1) ebusy enable busy interrupt es2 enable i 2 c-bus interrupt ecc enable closed caption interrupt et1 enable timer 1 interrupt ex1 enable external interrupt 1 et0 enable timer 0 interrupt ex0 enable external interrupt 0 2000 jun 30 19 philips semiconductors objective speci?cation enhanced tv microcontrollers with on-screen display (osd) saa56xx additional interrupt enable register (ien1) ex5 enable external interrupt 5 ex4 enable external interrupt 4 ex3 enable external interrupt 3 ex2 enable external interrupt 2 utx enable uart transmitter interrupt urx enable uart receiver interrupt uart enable uart transmitter/receiver interrupt et2 enable timer 2 interrupt interrupt priority register (ip) pbusy priority ebusy interrupt pes2 priority es2 interrupt pcc priority ecc interrupt pt1 priority timer 1 interrupt px1 priority external interrupt 1 pt0 priority timer 0 interrupt px0 priority external interrupt 0 additional interrupt priority register (ip1) px5 priority external interrupt 5 px4 priority external interrupt 4 px3 priority external interrupt 3 px2 priority external interrupt 2 putx priority uart transmitter interrupt purx priority uart receiver interrupt puart priority uart transmitter/receiver interrupt pt2 priority timer 2 interrupt port 0 (p0) p07 to p00 port 0 i/o register connected to external pins port 1 (p1) p17 to p10 port 1 i/o register connected to external pins port 2 (p2) p27 to p20 port 2 i/o register connected to external pins port 3 (p3) p34 to p30 port 3 i/o register connected to external pins bits function 2000 jun 30 20 philips semiconductors objective speci?cation enhanced tv microcontrollers with on-screen display (osd) saa56xx port 0 con?guration a (p0cfga) and port 0 con?guration b (p0cfgb) p0cfga<7:0> and p0cfgb<7:0> these two registers are used to con?gure port 0 lines. for example, the con?guration of port 0 pin 3 is controlled by setting bit 3 in both p0cfga and p0cfgb. p0cfgb 2000 jun 30 21 philips semiconductors objective speci?cation enhanced tv microcontrollers with on-screen display (osd) saa56xx program status word (psw) c carry bit ac auxiliary carry bit f0 ?ag 0 rs1 to rs0 register bank selector bits rs<1:0>: 00 = bank 0 (00h to 07h) 01 = bank 1 (08h to 0fh) 10 = bank 2 (10h to 17h) 11 = bank 3 (18h to 1fh) ov over?ow ?ag p parity bit pulse width modulator 0 control register (pwm0) pw0e activate this pwm and take control of respective port pin (logic 1) pw0v5 to pw0v0 pulse width modulator high time pulse width modulator 1 control register (pwm1) pw1e activate this pwm (logic 1) pw1v5 to pw1v0 pulse width modulator high time pulse width modulator 2 control register (pwm2) pw2e activate this pwm (logic 1) pw2v5 to pw2v0 pulse width modulator high time pulse width modulator 3 control register (pwm3) pw3e activate this pwm (logic 1) pw3v5 to pw3v0 pulse width modulator high time pulse width modulator 4 control register (pwm4) pw4e activate this pwm (logic 1) pw4v5 to pw4v0 pulse width modulator high time pulse width modulator 5 control register (pwm5) pw5e activate this pwm (logic 1) pw5v5 to pw5v0 pulse width modulator high time pulse width modulator 6 control register (pwm6) pw6e activate this pwm (logic 1) pw6v5 to pw6v0 pulse width modulator high time pulse width modulator 7 control register (pwm7) pw7e activate this pwm (logic 1) pw7v5 to pw7v0 pulse width modulator high time timer2 reload capture high byte (rcap2h) rcap2h7 to rcap2h0 timer 2 capture/reload high byte bits function 2000 jun 30 22 philips semiconductors objective speci?cation enhanced tv microcontrollers with on-screen display (osd) saa56xx timer2 reload capture low byte (rcap2l) rcap2l7 to rcap2l0 timer 2 capture/reload low byte rom bank (rombk) standby standby activation bit iic_lut1 to iic_lut0 i 2 c-bus lookup table selection; iic_lut<1:0>: 00 = p8xc558 normal mode 01 = p8xc558 fast mode 10 = p8xc558 slow mode 11 = reserved rambk1 to rambk0 ram bank selection bits rambk<1:0>: 00 = bank 0 (0 to 64 kbytes) 01 = bank 1 (64 to 128 kbytes) 10 = bank 2 (128 to 192 kbytes) 11 = bank 3 (192 to 256 kbytes) rombk2 to rombk0 rom bank selection bits rombk<2:0>: 000 = bank 0 (32 to 64 kbytes) 001 = bank 1 (64 to 96 kbytes) 010 = bank 2 (96 to 128 kbytes) 011 = bank 3 (128 to 160 kbytes) 100 = bank 4 (160 to 192 kbytes) 101 to 111 = reserved uart buffer (s0buf) s0buf7 to s0buf0 uart data buffer uart control register (s0con) sm0 to sm1 uart mode selection bits sm<0:1>: 00, shift register 01, 9-bit uart 10, 8-bit uart (variable baud rate) 11, 9-bit uart (variable baud rate) sm2 enables the multiprocessor communication feature in modes 2 and 3. in mode 2 or 3, if sm2 is set, then ri will not be activated, rb8 and s0buf will not be loaded if the received 9 th data bit is logic 0. in mode 1, if sm2 is set, then ri will not be activated, rb8 and s0buf will not be loaded if no valid stop bit was received. in mode 0, sm2 has no in?uence. ren enables serial reception. set by software to enable reception. cleared by software to disable reception. tb8 is the 9 th data bit that will be transmitted in modes 2 and 3. set or cleared by software as desired. rb8 in modes 2 and 3, rb8 is the 9 th data bit that was received. in mode 1, if sm2 is logic 0, rb8 is the stop bit that was received. in mode 0, rb8 is not used. loading of rb8 in modes 1, 2 and 3 depends on sm2. bits function 2000 jun 30 23 philips semiconductors objective speci?cation enhanced tv microcontrollers with on-screen display (osd) saa56xx ti is the transmit interrupt ?ag. set by hardware at the end of the 8 th bit time in mode 0, or at the beginning of the stop bit in the other modes. must be cleared by software. ri is the receive interrupt ?ag. set by hardware at the end of the 8 th bit time in mode 0, or halfway through the stop bit time in the other modes, in any serial reception (except see sm2). must be cleared by software. i 2 c-bus slave address register (s1adr) adr6 to adr0 i 2 c-bus slave address to which the device will respond gc enable i 2 c-bus general call address (logic 1) i 2 c-bus control register (s1con) cr2 to cr0 clock rate bits; cr<2:0>: 000 = 100 khz bit rate 001 = 3.75 khz bit rate 010 = 150 khz bit rate 011 = 200 khz bit rate 100 = 25 khz bit rate 101 = 1.875 khz bit rate 110 = 37.5 khz bit rate 111 = 50 khz bit rate ensi enable i 2 c-bus interface (logic 1) sta start ?ag. when this bit is set in slave mode, the hardware checks the i 2 c-bus and generates a start condition if the bus is free or after the bus becomes free. if the device operates in master mode, it will generate a repeated start condition. sto stop ?ag. if this bit is set in a master mode, a stop condition is generated. a stop condition detected on the i 2 c-bus clears this bit. this bit may also be set in slave mode, to recover from an error condition. in this case, no stop condition is generated to the i 2 c-bus, but the hardware releases the sda and scl lines and switches to the not selected receiver mode. the stop ?ag is cleared by the hardware. si serial interrupt ?ag. this ?ag is set and an interrupt request is generated, after any of the following events occur: a start condition is generated in master mode the own slave address has been received during aa = 1 the general call address has been received while s1adr.gc and aa = 1 a data byte has been received or transmitted in master mode (even if arbitration is lost) a data byte has been received or transmitted as selected slave a stop or start condition is received as selected slave receiver or transmitter. while the si ?ag is set, scl remains low and the serial transfer is suspended. si must be reset by software. bits function 2000 jun 30 24 philips semiconductors objective speci?cation enhanced tv microcontrollers with on-screen display (osd) saa56xx aa assert acknowledge ?ag. when this bit is set, an acknowledge is returned after any one of the following conditions: own slave address is received general call address is received (s1adr.gc = 1) a data byte is received, while the device is programmed to be a master receiver a data byte is received, while the device is selected slave receiver. when the bit is reset, no acknowledge is returned. consequently, no interrupt is requested when the own address or general call address is received. i 2 c-bus data register (s1dat) dat7 to dat0 i 2 c-bus data i 2 c-bus status register (s1sta) stat4 to stat0 i 2 c-bus interface status software adc register (sad) vhi analog input voltage greater than dac voltage (logic 1) ch1 to ch0 adc input channel select bits; ch<1:0>: 00 = adc3 01 = adc0 10 = adc1 11 = adc2 st (1) initiate voltage comparison between adc input channel and sad value sad7 to sad4 4 msbs of dac input word software adc control register (sadb) dc_comp enable dc comparator mode (logic 1) sad3 to sad0 4 lsbs of sad value stack pointer (sp) sp7 to sp0 stack pointer value timer/counter control register (tcon) tf1 timer 1 over?ow ?ag. set by hardware on timer/counter over?ow. cleared by hardware when processor vectors to interrupt routine. tr1 timer 1 run control bit. set/cleared by software to turn timer/counter on/off. tf0 timer 0 over?ow ?ag. set by hardware on timer/counter over?ow. cleared by hardware when processor vectors to interrupt routine. tr0 timer 0 run control bit. set/cleared by software to turn timer/counter on/off. ie1 interrupt 1 edge ?ag. both edges generate ?ag. set by hardware when external interrupt edge detected. cleared by hardware when interrupt processed. it1 interrupt 1 type control bit. set/cleared by software to specify edge/low level triggered external interrupts. ie0 interrupt 0 edge l ?ag. set by hardware when external interrupt edge detected. cleared by hardware when interrupt processed. it0 interrupt 0 type ?ag. set/cleared by software to specify falling edge/low level triggered external interrupts. bits function 2000 jun 30 25 philips semiconductors objective speci?cation enhanced tv microcontrollers with on-screen display (osd) saa56xx timer/counter2 control register (t2con) tf2 timer 2 over?ow ?ag. cleared by software. tf2 will not be set when either baud rate generation mode or clock out mode. exf2 timer 2 external flag. set on a negative transition on t2ex and exen2 = 1. in auto reload mode it is toggled on an under or over?ow. cleared by software. rclk0 receive clock 0 ?ag. when set, causes the uart to use timer 2 over?ow pulses. rclk0 = 0 causes timer 1 over?ow pulses to be used. tclk0 transmit clock 0 ?ag. when set, causes the uart to use timer 2 over?ow pulses. tclk0 = 0 causes timer 1 over?ow pulses to be used. exen2 timer 2 external enable ?ag. when set, allows a capture or reload to occur, together with an interrupt, as a result of a negative transition on input t2ex if in capture mode or auto reload mode with dcen reset. if in auto reload mode and dcen is set, this bit has no in?uence. in the other modes, exf2 is set and an interrupt is generated on a high-to-low transition on t2ex pin. in all modes, exen2 = 0 causes timer 2 to ignore events at t2ex. tr2 start/stop control bit. a logic 1 starts timer 2. c/ t2 counter timer selection bit. a logic 1 selects the counter for timer 2. cp/ rl2 capture/reload ?ag. selection of mode capture or reload. 14-bit pwm msb register (tdach) tpwe activate this 14-bit pwm (logic 1) td13 to td8 6 msbs of 14-bit number to be output by the 14-bit pwm 14-bit pwm lsb register (tdacl) td7 to td0 8 lsbs of 14-bit number to be output by the 14-bit pwm timer 0 high byte (th0) th07 to th00 8 msbs of timer 0 16-bit counter timer 1 high byte (th1) th17 to th10 8 msbs of timer 1 16-bit counter timer 2 high byte (th2) th27 to th20 8 msbs of timer 2 16-bit counter timer 0 low byte (tl0) tl07 to tl00 8 lsbs of timer 0 16-bit counter timer 1 low byte (tl1) tl17 to tl10 8 lsbs of timer 1 16-bit counter timer 2 low byte (tl2) tl27 to tl20 8 lsbs of timer 2 16-bit counter bits function 2000 jun 30 26 philips semiconductors objective speci?cation enhanced tv microcontrollers with on-screen display (osd) saa56xx timer/counter mode control (tmod) gate gating control timer/counter 1 c/ t counter/timer 1 selector m1 to m0 mode control bits timer/counter 1; m<1:0>: 00 = 8-bit timer or 8-bit counter with divide-by-32 prescaler 01 = 16-bit time interval or event counter 10 = 8-bit time interval or event counter with automatic reload upon overflow; reload value stored in th1 11 = stopped gate gating control timer/counter 0 c/ t counter/timer 0 selector m1 to m0 mode control bits timer/counter 0; m<1:0>: 00 = 8-bit timer or 8-bit counter with divide-by-32 prescaler 01 = 16-bit time interval or event counter 10 = 8-bit time interval or event counter with automatic reload upon overflow; reload value stored in th0 11 = one 8-bit time interval or event counter and one 8-bit time interval counter timer 2 mode control (t2mod) rclk1 receive clock 1 ?ag. when set, causes the uart to use timer 2 over?ow pulses. rclk1 = 0 causes timer 1 over?ow pulses to be used. tclk1 transmit clock 1 ?ag. when set, causes the uart to use timer 2 over?ow pulses. tclk1 = 0 causes timer 1 over?ow pulses to be used. t2rd timer 2 read ?ag. this bit is set by hardware if following tl2 read and before th2 read, th2 is incremented. it is reset on the trailing edge of next tl2 read. t2oe timer 2 output enable bit. when set, pin t2 is con?gured as a clock output. dcen down count enable ?ag. when set, this allows timer 2 to be con?gured as an up/down counter. text register 0 (txt0) x24 posn store packet 24 in extension packet memory (logic 0) or page memory (logic 1) display x24 display x24 from page memory (logic 0) or extension packet memory (logic 1) auto frame frame output switched off automatically if any video displayed (logic 1) disable header roll disable writing of rolling headers and time into memory (logic 1) display status row only display row 24 only (logic 1) disable frame frame output always low (logic 1) vps on enable capture of vps data (logic 1) inv on enable capture of inventory page in block 8 (logic 1) bits function 2000 jun 30 27 philips semiconductors objective speci?cation enhanced tv microcontrollers with on-screen display (osd) saa56xx text register 1 (txt1) ext pkt off disable acquisition of extension packets (logic 1) 8-bit disable checking of packets 0 to 24 written into memory (logic 1) acq off disable writing of data into display memory (logic 1) x26 off disable automatic processing of x/26 data (logic 1) full field acquire data on any tv line (logic 1) field polarity vsync pulse in second half of line during even ?eld (logic 1) h polarity hsync reference edge is negative going (logic 1) v polarity vsync reference edge is negative going (logic 1) text register 2 (txt2) acq bank select acquisition bank 1 (logic 1) req3 to req0 page request sc2 to sc0 start column of page request text register 3 (txt3) prd4 to prd0 page request data text register 4 (txt4) osd bank enable alternate osd location available via graphic attribute, additional 32 locations (logic 1) quad width enable enable display of quadruple width characters (logic 1) east/ west eastern language selection of character codes a0h to ffh (logic 1) disable double height disable normal decoding of double height characters (logic 1) b mesh enable enable meshing of black background (logic 1) c mesh enable enable meshing of coloured background (logic 1) trans enable display black background as video (logic 1) shadow enable display shadow/fringe (default se black) (logic 1) text register 5 (txt5) bkgnd out background colour displayed outside teletext boxes (logic 1) bkgnd in background colour displayed inside teletext boxes (logic 1) cor out cor active outside teletext and osd boxes (logic 1) cor in cor active inside teletext and osd boxes (logic 1) text out text displayed outside teletext boxes (logic 1) text in text displayed inside teletext boxes (logic 1) picture on out video displayed outside teletext boxes (logic 1) picture on in video displayed inside teletext boxes (logic 1) bits function 2000 jun 30 28 philips semiconductors objective speci?cation enhanced tv microcontrollers with on-screen display (osd) saa56xx text register 6 (txt6) bkgnd out background colour displayed outside teletext boxes (logic 1) bkgnd in background colour displayed inside teletext boxes (logic 1) cor out cor active outside teletext and osd boxes (logic 1) cor in cor active inside teletext and osd boxes (logic 1) text out text displayed outside teletext boxes (logic 1) text in text displayed inside teletext boxes (logic 1) picture on out video displayed outside teletext boxes (logic 1) picture on in video displayed inside teletext boxes (logic 1) text register 7 (txt7) status row top display memory row 24 information above teletext page (on display row 0) (logic 1) cursor on display cursor at position given by txt9 and txt10 (logic 1) reveal display characters in area with conceal attribute set (logic 1) bottom/ t op display memory rows 12 to 23 when double height height bit is set (logic 1) double height display each character as twice normal height (logic 1) box on 24 enable display of teletext boxes in memory row 24 (logic 1) box on 1 to 23 enable display of teletext boxes in memory row 1 to 23 (logic 1) box on 0 enable display of teletext boxes in memory row 0 (logic 1) text register 8 (txt8) flicker st op on disable flicker stopper circuit (logic 1) disable spanish disable special treatment of spanish packet 26 characters (logic 1) pkt 26 received (2) packet 26 data has been processed (logic 1) wss received (2) wss data has been processed (logic 1) wss on enable acquisition of wss data (logic 1) cvbs1/ cvbs0 select cvbs1 as source for device (logic 1) text register 9 (txt9) cursor freeze lock cursor at current position (logic 1) clear memory (1) clear memory block pointed to by txt15 (logic 1) a0 access extension packet memory (logic 1) r4 to r0 (3) current memory row value text register 10 (txt10) c5 to c0 (4) current memory column value text register 11 (txt11) d7 to d0 data value written or read from memory location de?ned by txt9, txt10 and txt15 bits function 2000 jun 30 29 philips semiconductors objective speci?cation enhanced tv microcontrollers with on-screen display (osd) saa56xx text register 12 (txt12) 525/ 625 sync 525-line cvbs signal is being received (logic 1) spanish spanish character set present (logic 1) rom ver3 to rom ver0 mask programmable identi?cation for character set video signal quality acquisition can be synchronized to cvbs (logic 1) text register 13 (txt13) vps received vps data (logic 1) page clearing software or power-on page clear in progress (logic 1) 525 display 525-line synchronisation for display (logic 1) 525 text 525-line wst being received (logic 1) 625 text 625-line wst being received (logic 1) pkt 8/30 packet 8/30/x(625) or packet 4/30/x(525) data detected (logic 1) fastext packet x/27 data detected (logic 1) text register 14 (txt14) display bank upper bank for display selected (logic 1) page3 to page0 current display page text register 15 (txt15) micro bank upper bank for micro selected (logic 1) block3 to block0 current micro block to be accessed by txt9, txt10 and txt11 text register 17 (txt17) force acq1 to force acq0 force acq<1:0>: 00 = automatic selection 01 = force 525 timing, force 525 teletext standard 10 = force 625 timing, force 625 teletext standard 11 = force 625 timing, force 525 teletext standard force disp1 to force disp0 force disp<1:0>: 00 = automatic selection 01 = force display to 525 mode (9 lines per row) 10 = force display to 625 mode (10 lines per row) 11 = not valid (default to 625) screen col2 to screen col0 de?nes colour to be displayed instead of tv picture and black background; these bits <2:0> are equivalent to the rgb components. screen col<2:0>: 000 = transparent 001 = clut entry 9 010 = clut entry 10 011 = clut entry 11 100 = clut entry 12 101 = clut entry 13 110 = clut entry 14 111 = clut entry 15 bits function 2000 jun 30 30 philips semiconductors objective speci?cation enhanced tv microcontrollers with on-screen display (osd) saa56xx text register 18 (txt18) not3 to not0 national option table selection, maximum of 31 when used with east/ west bit bs1 to bs0 basic character set selection text register 19 (txt19) ten enable twist character set (logic 1) tc2 to tc0 language control bits (c12/c13/c14) that has twisted character set ts1 to ts0 twist character set selection text register 20 (txt20) drcs enable re-map column 8/9 to drcs (txt and cc modes) (logic 1) osd planes character code columns 8 and 9 de?ned as double plane characters (special graphics characters) (logic 1) extended special graphics extended special graphics disabled (columns 8 and 9 only used for special graphics characters) (logic 0) extended special graphics enabled (user de?nable range for special graphics characters) (logic 1) char select enable enables character set selection in cc display mode (logic 1) osd lang enable enable use of osd lan<2:0> to de?ne language option for display, instead of c12/c13/c14 osd lan2 to osd lan0 alternative c12/c13/c14 bits for use with osd menus text register 21 (txt21) disp lines1 to disp lines0 the number of display lines per character row; disp lines<1:0>: 00 = 10 lines per character (defaults to 9 lines in 525 mode) 01 = 13 lines per character 10 = 16 lines per character 11 = reserved char size1 to char size0 character matrix size bits; char size<1:0>: 00 = 10 lines per character (matrix 12 10) 01 = 13 lines per character (matrix 12 13) 10 = 16 lines per character (matrix 12 16) 11 = reserved i 2 c port 1 enable i 2 c-bus port 1 selection (p1.5/sda1 and p1.4/scl1) (logic 1) ccon closed caption acquisition on (logic 1) i 2 c port 0 enable i 2 c-bus port 0 selection (p1.7/sda0 and p1.6/scl0) (logic 1) cc/txt display con?gured for cc mode (logic 1) bits function 2000 jun 30 31 philips semiconductors objective speci?cation enhanced tv microcontrollers with on-screen display (osd) saa56xx text register 22 (txt22) gpf7 to gpf6 reserved gpf5 to gpf4 and gpf2 to gpf0 general purpose register, bits de?ned by mask programmable bits (character rom address 09feh) gpf3 pwm0, pwm1, pwm2 and pwm3 output on port 3.0 to port 3.3 respectively (logic 0) pwm0, pwm1, pwm2 and pwm3 output on port 2.1 to port 2.4 respectively (logic 1) text register 23 (txt23) not b3 to not b0 national option table selection for page b, maximum of 32 when used with east/ west b bit east/ west b eastern language selection of character codes a0h to ffh for page b (logic 1) drcs b enable normal osd characters used on page b (logic 0) re-map column 8/9 to drcs (txt and cc modes) on page b (logic 1) bs b1 to bs b0 basic character set selection for page b text register 24 (txt24) bkgnd out b background colour displayed outside teletext boxes (teletext page) (logic 1) bkgnd in b background colour displayed inside teletext boxes (teletext page) (logic 1) cor out b cor active outside teletext and osd boxes (teletext page) (logic 1) cor in b cor active inside teletext and osd boxes (teletext page) (logic 1) text out b text displayed outside teletext boxes (teletext page) (logic 1) text in b text displayed inside teletext boxes (teletext page) (logic 1) picture on out b video displayed outside teletext boxes (teletext page) (logic 1) picture on in b video displayed inside teletext boxes (teletext page) (logic 1) text register 25 (txt25) bkgnd out b background colour displayed outside teletext boxes (sub-title/news?ash page) (logic 1) bkgnd in b background colour displayed inside teletext boxes (sub-title/news?ash page) (logic 1) cor out b cor active outside teletext and osd boxes (sub-title/news?ash page) (logic 1) cor in b cor active inside teletext and osd boxes (sub-title/news?ash page) (logic 1) text out b text displayed outside teletext boxes (sub-title/news?ash page) (logic 1) text in b text displayed inside teletext boxes (sub-title/news?ash page) (logic 1) picture on out b video displayed outside teletext boxes (sub-title/news?ash page) (logic 1) picture on in b video displayed inside teletext boxes (sub-title/news?ash page) (logic 1) bits function 2000 jun 30 32 philips semiconductors objective speci?cation enhanced tv microcontrollers with on-screen display (osd) saa56xx text register 26 (txt26) extended drcs columns 8/9 mapped to drcs when drcs characters enabled (32 drcs characters) (logic 0) columns 8/9/a/c mapped to drcs when drcs characters enabled (64 drcs characters) (logic 1) trans enable b display black background as video on page b (logic 1) c mesh enable b enable meshing of coloured background on page b (logic 1) b mesh enable b enable meshing of black background on page b (logic 1) shadow enable b disable display of shadow/fringing on page b (logic 0) display shadow/ fringe (default se black) on page b (logic 1) box on 24 b enable display of teletext boxes in memory row 24 of page b (logic 1) box on 1 b to 23 b enable display of teletext boxes in memory row 1 to 23 of page b (logic 1) box on 0 b enable display of teletext boxes in memory row 0 of page b (logic 1) text register 27 (txt27) scrb2 to scrb0 de?nes colour to be displayed instead of tv picture and black background for page b; these bits are equivalent to the rgb components. scrb<2:0>: 000 = transparent 001 = clut entry 9 010 = clut entry 10 011 = clut entry 11 100 = clut entry 12 101 = clut entry 13 110 = clut entry 14 111 = clut entry 15 text register 28 (txt28) multi-page conventional internal memory storage of acquisition data (logic 0) enables multi-page acquisition operation for software controlled storage of acquired data in external sram (logic 1) cc/txt b display page b con?gured for cc mode (logic 1) active page display page b active during two page mode (logic 1) display bank b select upper bank for display page b (logic 1) page b3 to page b0 current display page for page b bits function 2000 jun 30 33 philips semiconductors objective speci?cation enhanced tv microcontrollers with on-screen display (osd) saa56xx text register 29 (txt29) ten b disable twist function for page b (logic 0) enable twist character set for page b (logic 1) ts b1 to ts b0 twist character set selection for page b osd planes b character code columns 8 and 9 de?ned as single plane characters for display page b (logic 0) character code columns 8 and 9 de?ned as double plane characters (special graphics characters) for display page b (logic 1) osd lang enable b enable use of osd lan b<2:0> to de?ne language option for display, instead of c12/c13/c14 for display page b osd lan b2 to osd lan b0 alternative c12/c13/c14 bits for use with osd menus for display page b text register 30 (txt30) tc b2 to tc b0 language control bits (c12/c13/c14) that has twist character set for page b bottom/top b display memory rows 0 to 11 when double height bit is set on display page b (logic 0) display memory rows 12 to 23 when double height bit is set on display page b (logic 1) double height b display each character as twice normal height on display page b (logic 1) status row top b display memory row 24 information below teletext page (on display row 24) on display page b (logic 0) display memory row 24 information above teletext page (on display row 0) on display page b (logic 1) dislay x24 b display row 24 from basic page memory on display page b (logic 0) display row 24 from appropriate location in extension memory on display page b (logic 1) display status row only b display only row 24 on display page b (logic 1) text register 31 (txt31) gpf11 to gpf10 general purpose register, bits de?ned by mask programmable location (character rom address 09feh) gpf9 to gpf8 00 = 80c51 configured for 6 mhz operation 01 = 80c51 configured for 12 mhz operation 10 = reserved 11 = 80c51 configured for 6 mhz operation text register 32 (txt32) 9fe11 reserved 9ff11 to 9ff5 mask programmable bits available for uoc con?guration (character rom address 09ffh) text register 33 (txt33) bfe7 to bfe0 mask programmable bits available for uoc con?guration (character rom address 0bfeh) text register 34 (txt34) bfe11 to bfe8 mask programmable bits available for uoc con?guration (character rom address 0bfeh) bits function 2000 jun 30 34 philips semiconductors objective speci?cation enhanced tv microcontrollers with on-screen display (osd) saa56xx notes 1. this flag is set by software and reset by hardware. 2. this flag is set by hardware and must be reset by software. 3. valid range txt mode 0 to 24. 4. valid range txt mode 0 to 39. 5. must be set to 55h to disable watchdog timer when active. text register 35 (txt35) pkt1-24<7:0> teletext packets 1-24 received for blocks 7 to 0, set by hardware and cleared by software. teletext packets 1-24 received after a header in any one vertical blanking interval (vbi) (logic 1) text register 36 (txt36) pkt1-24<9:8> teletext packets 1-24 received for blocks 9 to 8, set by hardware and cleared by software. teletext packets 1-24 received after a header in any one vbi (logic 1) watchdog timer (wdt) wdv7 to wdv0 watchdog timer period watchdog timer key (wdtkey) wkey7 to wkey0 (5) watchdog timer key wide screen signalling 1 (wss1) wss<3:0> error error in wss<3:0> (logic 1) wss3 to wss0 signalling bits to de?ne aspect ratio (group 1) wide screen signalling 2 (wss2) wss<7:4> error error in wss<7:4> (logic 1) wss7 to wss4 signalling bits to de?ne enhanced services (group 2) wide screen signalling 3 (wss3) wss<13:11> error error in wss<13:11> (logic 1) wss13 to wss11 signalling bits to de?ne reserved elements (group 4) wss<10:8> error error in wss<10:8> (logic 1) wss10 to wss8 signalling bits to de?ne subtitles (group 3) external ram pointer (xramp) xramp7 to xramp0 upper address byte for movx ram space in direct addressing. to use with one of the r0 to r7 registers to provide the lower address byte. bits function 2000 jun 30 35 philips semiconductors objective speci?cation enhanced tv microcontrollers with on-screen display (osd) saa56xx 8.6 character set feature bits features available on the saa56xx devices are reflected in a specific area of the character rom. these sections of the character rom are mapped to two special function registers: txt22 and txt12. character rom address 09feh is mapped to sfr txt22, as shown in table 6 and described in table 7. character rom address 09ffh is mapped to sfr txt12, as shown in table 8 and described in table 9. table 6 character rom - txt22 mapping table 7 description of character rom address 09feh bits table 8 character rom - txt12 mapping table 9 description of character rom address 09ffh bits mapped items 11 10 9 8 7 6 5 4 3 2 1 0 character rom; address 09feh xxxxxxxxuxxx mapped to txt22 ---- 76543210 u = used, x = reserved bit function 0 to 2 reserved 3 1 = pwm0, pwm1, pwm2 and pwm3 output routed to port 2.1 to port 2.4 respectively 0 = pwm0, pwm1, pwm2 and pwm3 output routed to port 3.0 to port 3.3 respectively 4 to 11 reserved mapped items 11 10 9 8 7 6 5 4 3 2 1 0 character rom; address 09ffh xxxxxxxuxxxx mapped to txt12 ------- 65432 u = used, x = reserved bit function 4 1 = spanish character set present 0 = no spanish character set present 0 to 3, 5 to 11 reserved 2000 jun 30 36 philips semiconductors objective speci?cation enhanced tv microcontrollers with on-screen display (osd) saa56xx 8.7 movx memory the normal 80c51 external memory area has been mapped internally to the device (see fig.8). this means that the movx instruction accesses memory internal to the device. 8.7.1 movx space page selection the movx ram page pointer is used to select one of the 256 pages within the movx address space, not all pages are allocated, refer to fig.9 for further detail. a page consists of 256 consecutive bytes. xramp only works with internal movx memory. handbook, full pagewidth gsa021 dynamically redefinable characters display ram for closed caption (4) address range 8460h to 84ffh "additional internal data ram" upper 32 kbytes lower 32 kbytes display registers 8fffh 9000h ffffh 8800h 87ffh 87e0h clut 871fh 8700h 845fh 8000h display ram for text pages (1) data ram (2) 6fffh 7000h 7fffh 2000h 1fffh 0800h 07ffh 0000h (3) fig.8 movx ram allocation. (1) both saa56xx 128 and 192 kbytes have 12 kbytes of display memory. (2) 0800h to 1fffh are mapped into 6 kbytes of bank 0 of external ram. an external ram is required to be able to address this memory space (refer to section 20 and section 29.2). (3) both saa56xx 128 and 192 kbytes have 2 kbytes of data ram. (4) display ram for closed caption and text is shared. 2000 jun 30 37 philips semiconductors objective speci?cation enhanced tv microcontrollers with on-screen display (osd) saa56xx handbook, full pagewidth gsa070 xramp sfr = 00h ffh 00h xramp sfr = 01h ffh 00h 0000h 00ffh 0100h 01ffh xramp sfr = feh movx @ dptr,a movx a, @ dptr movx @ ri,a movx a, @ ri ffh 00h 0800h 08ffh allocated (1) allocated (1) not allocated not allocated xramp sfr = ffh ffh 00h 2000h 20ffh xramp sfr = ffh ffh 00h 4000h 4fffh xramp sfr = ffh ffh 00h ff00h ffffh fig.9 indirect addressing of movx ram. (1) internal 14-kbyte data and display ram of the device. 9 power-on reset two reset inputs are present on the device, the reset pin being active high and reset pin being active low. only one of these inputs need be connected in the system as they are ored internally to the device and each pin has the necessary pull-down (for reset) and pull-up (for reset) resistors at the pad. an automatic reset can be obtained when v dd is switched on by connecting the reset pin to v ddp through a 10 m f capacitor, providing the v dd rise time does not exceed 1 ms, and the oscillator start-up time does not exceed 10 ms. alternatively, a capacitor connected to v ssp with a suitable pull-up (to v ddp ) (e.g. 10 m f capacitor; 16 k w resistor) can be connected to the reset pin. to ensure correct initialisation, the reset/ reset pin must be held high/low long enough for the oscillator to settle following power-up, usually a few milliseconds (application specific, typically 10 ms). once the oscillator is stable, a further 24 crystal clocks are required to generate the reset. once the above reset condition has been detected, an internal reset signal is triggered (which remains active for 2048 clock cycles). 2000 jun 30 38 philips semiconductors objective speci?cation enhanced tv microcontrollers with on-screen display (osd) saa56xx 10 power saving modes of operation three power saving modes are incorporated in the saa56xx device: standby, idle and power down. when utilizing one of these modes, power to the device (v ddp , v ddc and v dda ) should be maintained, since power saving is achieved by clock gating on a section by section basis. 10.1 standby mode during standby mode, the acquisition and display sections of the device are disabled. the following functions remain active: 80c51 cpu core memory interface i 2 c timer/counters watchdog timer uart, sad, pwms. to enter standby mode, the standby bit in the rombk register must be set. once in standby, the crystal oscillator continues to run, but the internal clocks to acquisition and display are gated out. however, the clocks to the 80c51 cpu core, memory interface, i 2 c-bus, uart, timer/counters, watchdog timer and pulse width modulators are maintained. since the output values on rgb and vds are maintained, the display output must be disabled before entering this mode. the standby mode may be used in conjunction with both idle and power down modes. hence, prior to entering either idle or power down, the standby bit may be set, thus allowing wake-up of the 80c51 cpu core without fully waking the entire device. (this enables detection of a remote control source in a power saving mode.) 10.2 idle mode during idle mode, acquisition, display and the cpu sections of the device are disabled. the following functions remain active: memory interface i 2 c-bus timer/counters watchdog timer uart, sad, pwms. to enter idle mode, bit idl in the pcon register must be set. the watchdog timer must be disabled prior to entering idle to prevent the device being reset. once in idle mode, the crystal oscillator continues to run, but the internal clock to the cpu, acquisition and display are gated out. however, the clocks to the memory interface, i 2 c-bus, timer/counters, watchdog timer and pulse width modulators are maintained. the cpu state is frozen along with the status of all sfrs. internal ram contents are maintained, as are the device output pin values. since the output values on rgb and vds are maintained, the display output must be disabled before entering this mode. there are three methods available to recover from idle: assertion of an enabled interrupt will cause bit idl to be cleared by hardware, thus terminating idle mode. the interrupt is serviced and, following the instruction reti, the next instruction to be executed will be the one after the instruction that put the device into idle mode. a second method of exiting idle is via an interrupt generated by the sad dc compare circuit. when the saa56xx is configured in this mode, detection of an analog threshold at the input to the sad may be used to trigger wake-up of the device i.e. tv front panel key-press. as above, the interrupt is serviced, and following the instruction reti, the next instruction to be executed will be the one following the instruction that put the device into idle. the third method of terminating idle mode is with an external hardware reset. since the oscillator is running, the hardware reset need only be active for 24 crystal clocks at 12 mhz to complete the reset operation. reset defines all sfrs and display memory to a pre-defined state, but maintains all other ram values. code execution commences with the program counter set to 0000. 10.3 power down mode in power down mode, the crystal oscillator is stopped. the contents of all sfrs and data memory are maintained, however, the contents of the auxiliary/display memory are lost. the port pins maintain the values defined by their associated sfrs. since the output values on rgb and vds are maintained, the display output must be made inactive before entering power down mode. the power down mode is activated by setting bit pd in the pcon register. it is advised to disable the watchdog timer prior to entering power down. recovery from power down takes several milliseconds as the oscillator must be given time to stabilize. 2000 jun 30 39 philips semiconductors objective speci?cation enhanced tv microcontrollers with on-screen display (osd) saa56xx there are three methods of exiting power down: external interrupt. since the clock is stopped, an external interrupt needs to be set level sensitive prior to entering power down. the interrupt is serviced and, following the instruction reti, the next instruction to be executed will be the one after the instruction that put the device into power down mode. interrupt generated by the sad dc compare circuit. when saa56xx is configured in this mode, detection of a certain analog threshold at the input to the sad may be used to trigger wake-up of the device, i.e. tv front panel key-press. as above, the interrupt is serviced and, following the instruction reti, the next instruction to be executed will be the one following the instruction that put the device into power down. external hardware reset. this reset defines all sfrs and display memory, but maintains all other ram values. code execution commences with the program counter set to 0000. 11 i/o facility the saa56xx devices have 32 i/o lines, each of which can be individually addressed, or form four parallel 8-bit addressable ports: port 0, port 1, port 2 and port 3. i 2 c-bus ports (p1.4, p1.5, p1.6 and p1.7) can only be configured as open-drain. 11.1 port type all individual ports can be programmed to function in one of four modes, the mode is defined by two associated port configuration registers: pncfga and pncfgb (where n = port number 0, 1, 2 or 3). the modes available are open-drain, quasi-bidirectional, high-impedance and push-pull. 11.1.1 o pen - drain (ttl, 5 v t olerant ) the open-drain mode can be used for bidirectional operation of a port and requires an external pull-up resistor. the pull-up voltage has a maximum value of 5.5 v, to allow connection of the device into a 5 v environment. 11.1.2 q uasi - bidirectional (cmos, 3v3 t olerant ) the quasi-bidirectional mode is a combination of open-drain and push-pull. it requires an external pull-up resistor to v ddp (normally 3.3 v). when a low-to-high signal transition is output from the device, the pad is put into push-pull mode for one clock cycle (166 ns) after which the pad goes into open-drain mode. this mode is used to speed up the edges of signal transitions. this is the default mode of operation of the pads after reset. 11.1.3 h igh - impedance (ttl, 5 v t olerant ) the high-impedance mode can be used for input-only operation of the port. when using this configuration, the two output transistors are turned off. 11.1.4 p ush - pull (cmos, 3v3 t olerant ) the push-pull mode can be used for output only. in this mode, the signal is driven to either 0 v or v ddp , which is nominally 3.3 v. 12 interrupt system the device has 15 interrupt sources, each of which can be enabled or disabled. when enabled, each interrupt can be assigned one of two priority levels. there are five interrupts that are common to the 80c51. two of these are external interrupts (ex0 and ex1); the other three are timer interrupts (et0, et1 and et2). in addition to the conventional 80c51, two application specific interrupts are incorporated internal to the device, with the following functionality: closed caption data ready interrupt (ecc). this interrupt is generated when the device is configured in closed caption acquisition mode. the interrupt is activated at the end of the currently selected slice line, as defined in the cclin sfr. display busy interrupt (ebusy). an interrupt is generated when the display enters either a horizontal or vertical blanking period. i.e. indicates when the microcontroller can update the display ram without causing undesired effects on the screen. this interrupt can be configured in one of two modes using the memory mapped register (mmr) configuration register (address 87ffh, bit txt/v). C text display busy: an interrupt is generated on each active horizontal display line when the horizontal blanking period is entered. C vertical display busy: an interrupt is generated on each vertical display field when the vertical blanking period is entered. 2000 jun 30 40 philips semiconductors objective speci?cation enhanced tv microcontrollers with on-screen display (osd) saa56xx there are four interrupts connected to the 80c51 microcontroller peripherals, as follows: i 2 c-bus transmit/receive uart receive uart transmit uart receive/transmit. four additional general purpose external interrupts are incorporated in the saa56xx with programmable edge detection (int2 {ex2}, int3 {ex3}, int4 {ex4} and int5 {ex5}). the extint sfr is used to configure each of these interrupts as either level activated, rising edge, falling edge or both edges sensitive, see table 10. 12.1 interrupt enable structure each of the individual interrupts can be enabled or disabled by setting or clearing the relevant bit in the interrupt enable sfrs (ie and ien1). all interrupt sources can also be globally disabled by clearing bit ea (ie.7), as shown in fig.10. 12.2 interrupt enable priority each interrupt source can be assigned one of two priority levels. the interrupt priorities are defined by the interrupt priority sfrs (ip and ip1). a low priority interrupt can be interrupted by a high priority interrupt, but not by another low priority interrupt. a high priority interrupt cannot be interrupted by any other interrupt source. if two requests of different priority level are received simultaneously, the request with the higher priority level is serviced. if requests of the same priority level are received simultaneously, an internal polling sequence determines which request is serviced. thus, within each priority level there is a second priority structure determined by the polling sequence as defined in table 12. 12.3 interrupt vector address the processor acknowledges an interrupt request by executing a hardware generated lcall to the appropriate servicing routine. the interrupt vector addresses for each source are shown in table 12. 12.4 level/edge interrupt the external interrupt can be programmed to be either level activated or transition activated by setting or clearing the it0/it1 bits in the timer control sfr (tcon), see table 11. the external interrupt int1 differs from the standard 80c51 interrupt in that it is activated on both edges when in edge sensitive mode. this is to allow software pulse width measurement for handling remote control inputs. the four other external interrupts int2, int3, int4 and int5 are configured using the extint register, as shown in table 10. table 10 con?guration of external interrupts (int2 to int5) table 11 external interrupt activation table 12 interrupt priority (within same level) sfr extint; exncfg<1:0>; n=2to5 mode 00 level sensitive - active low 01 rising edge sensitive 10 falling edge sensitive 11 both edges sensitive bit level edge it0 active low it1 - int0 = negative edge int1 = positive and negative edge source priority within level interrup t vector related sfrs ex0 highest 0003h ie es2 002bh ie eurx 0053h ien1 et0 000bh ie ebusy 0033h ie ex2 005bh ien1 ex1 0013h ie et2 003bh ien1 ex3 0063h ien1 et1 001bh ie euart 0043h ien1 ex4 006bh ien1 ecc 0023h ie eutx 004bh ien1 ex5 lowest 0073h ien1 2000 jun 30 41 philips semiconductors objective speci?cation enhanced tv microcontrollers with on-screen display (osd) saa56xx handbook, full pagewidth priority control sfr ip < 0:6 > sfr ip1 < 0:7 > global enable sfr ie.7 source enable sfr ie < 0:6 > sfr ien1 < 0:7 > interrupt source gsa074 l1 h1 highest priority level 0 highest priority level 1 ex0 lowest priority level 0 lowest priority level 1 es2 l2 h2 eurx l3 h3 et0 l4 h4 ebusy l5 h5 ex2 l6 h6 ex1 l7 h7 et2 l8 h8 ex3 l9 h9 et1 l10 h10 euart l11 h11 ex4 l12 h12 ecc l13 h13 eutx l14 h14 ex5 l15 h15 fig.10 interrupt structure. 2000 jun 30 42 philips semiconductors objective speci?cation enhanced tv microcontrollers with on-screen display (osd) saa56xx 13 timers/counters three 16-bit timers/counters are incorporated: timer 0, timer 1 and timer 2. each can be configured to operate as either timers or event counters. when the timers/counters are configured as timers, the period will vary depending on the chosen microcontroller clock frequency. sfr txt31 may be used by software to determine the selected microcontroller clock frequency for period adjustment. in timer mode, the register is incremented on every machine cycle, so that machine cycles are counted. since the machine cycle consists of six oscillator periods, the count rate is 1 6 f clk (where f clk is the microcontroller clock frequency: 6 or 12 mhz). in counter mode, the register is incremented in response to a negative transition at its corresponding external pin t0/1/2. since pins t0/1/2 are sampled once per machine cycle, it takes two machine cycles to recognise a transition. this gives a maximum count rate of 1 12 f clk (where f clk is the microcontroller clock frequency, 6 or 12 mhz). 13.1 timer/counter 0 and timer/counter 1 there are six special function registers used to control timer/counter 0 and timer/counter 1: table 13 timer/counter 0 and timer/counter 1 registers the timer/counter function is selected by control bits c/t in the timer mode sfr(tmod). these two timers/counters have four operating modes, which are selected by bit-pairs (m1 and m0) in tmod. detail of the modes of operation is given in handbook ic20, 80c51-based 8-bit microcontrollers . tl0 and th0 are the actual timer/counter registers for timer 0. tl0 is the low byte and th0 is the high byte. tl1 and th1 are the actual timer/counter registers for timer 1. tl1 is the low byte and th1 is the high byte. 13.2 timer/counter 2 timer 2 is controlled using the following sfrs: table 14 timer 2 special function registers timer 2 can operate in four different modes (see table 15): auto-reload capture baud rate generation clock output. the count-down option is only possible in the auto-reload mode with dcen in t2mod set and the external trigger input disabled. table 15 timer 2 operating mode 13.2.1 c apture mode in the capture mode, registers rcap2l/rcap2h are used to capture the tl2/th2 data. by setting/clearing bit exen2 in t2con, the external trigger input t2ex (p3.4) can be enabled/disabled. if exen2 = 0, timer 2 is a 16-bit timer/counter which, upon overflow, sets tf2 flag in t2con. if exen2 = 1, then timer 2 does the above, but with the added feature that a high-to-low transition at t2ex on port 3.4 causes the current timer 2 value (tl2/th2 data) to be captured into rcap2l/rap2h, and bit exf2 in t2con to be set. sfr address tcon 88h tmod 89h tl0 8ah th0 8bh tl1 8ch th1 8dh sfr address t2con f1h t2mod f2h rcap2l f3h rcap2h f4h tl2 f5h th2 f6h rclk0 or tclk0 or rclk1 or tclk1 cp/ rl2 t2oe c/ t2 operating mode 0 0 0 x 16-bit auto-reload 0 1 0 x 16-bit capture 1 x x x baud rate generation x 0 1 0 clock output 2000 jun 30 43 philips semiconductors objective speci?cation enhanced tv microcontrollers with on-screen display (osd) saa56xx 13.2.2 a uto - reload mode in the auto-reload mode, timer 2 can be programmed to count up/down by clearing/setting bit dcen in t2mod. 13.2.3 c ounting up (dcen = 0) in the auto-reload mode and when counting up, registers rcap2l/rcap2h are used to hold a reload value for tl2/th2 when timer 2 rolls over. by setting/clearing bit exen2 in t2con, external trigger t2ex on port 3.4 can be enabled/disabled. if exen2 = 0, timer 2 is a 16-bit timer/counter which, upon overflow, sets tf2 and reloads tl2/th2 with the reload value in rcap2l/rcap2h. if exen2 = 1, timer 2 does the above, but with the added feature that a high-to-low transition at the external trigger t2ex on port 3.4 causes the current rcap2l/rcap2h value to be loaded into tl2/th2 respectively, and bit exf2 in t2con to be set. timer 2 interrupt is set if exf2 is set or tf2 is set. 13.2.4 c ounting up (dcen = 1 and t2ex = 1) in this mode timer 2 counts up. when timer 2 overflows (ffffh state), bit tf2 is set. this reloads tl2 and th2 with the contents of rcap2l and rcap2h, respectively. on overflow, bit exf2 is inverted and hence toggles during operation, so that bit exf2 can be used as 17 th bit, if desired. timer 2 interrupt will be set only if tf2 is set. 13.2.5 c ounting down (dcen = 1 and t2ex = 0) in this mode timer 2 counts down. underflow will occur when the contents of tl2/th2 match the contents of rcap2l/rcap2h. a timer 2 roll over from 0000h to ffffh is not considered as an underflow. upon underflow, bit tf2 will be set and registers tl2/th2 will be loaded with ffffh. in addition, an underflow will cause bit exf2 to be inverted, such that it can be used as the 17 th bit, if desired. timer 2 interrupt is set only if tf2 is set. 13.2.6 b aud rate generation mode in this mode, timer overflow will load tl2 and th2 with the contents of t2capl and t2caph respectively and it will not set tf2. bit exf2 will be set if exen2 is set and a high-to-low transition is detected on pin t2ex (port 3.4). when timer 2 is configured for timer operation, the timer increments every state. normally, as a timer, it would increment every machine cycle. timer 2 interrupt is set only if exf2 is set. 13.2.7 c lock output mode in the clock output mode, external pin t2 is used as a clock output. a timer overflow causes tl2 and th2 to be loaded with t2capl and t2caph, respectively. an overflow toggles bit exf2, which is connected to pin t2. the frequency of t2 will be half the overflow frequency. timer overflow will not set tf2. a high-to-low transition on the external trigger t2ex on port 3.4 sets exf2. it is possible to configure timer 2 in clock-out mode and baud generator mode simultaneously. timer 2 interrupt is set only if exf2 is set. 14 watchdog timer the watchdog timer is a counter that, once in an overflow state, forces the microcontroller into a reset condition. the purpose of the watchdog timer is to reset the microcontroller if it enters an erroneous processor state (possibly caused by electrical noise or rfi) within a reasonable period of time. when enabled, the watchdog circuit generates a system reset if the user program fails to reload the watchdog timer within a specified length of time, known as the watchdog interval. this interval varies, depending on the chosen microcontroller clock frequency. the watchdog timer consists of an 8-bit counter with an 16-bit prescaler. the prescaler is fed with a signal whose frequency is 1 6 f clk (1 mhz for 6 mhz 80c51 core). the 8-bit counter is incremented every t seconds where: or t6 1 f clk ------- - ? ?? 2 16 6 65536 6 mhz ------------------------- - = 65.53 ms == 6 65536 12 mhz ------------------------- - 32.768 ms = 2000 jun 30 44 philips semiconductors objective speci?cation enhanced tv microcontrollers with on-screen display (osd) saa56xx 14.1 watchdog timer operation the watchdog timer operation is activated when bit wle in the power control sfr (pcon) is set. the watchdog can be disabled by software by loading the value 55h into the watchdog timer key sfr (wdtkey). this must be performed before entering idle/power-down mode to prevent exiting the mode prematurely. once activated, the watchdog timer sfr (wdt) must be reloaded before the timer overflows. bit wle must be set to enable loading of the wdt sfr. once loaded, bit wle is reset by hardware, to prevent erroneous software from loading the wdt sfr. the value loaded into the wdt defines the watchdog interval (wi): for 6 mhz microcontroller clock, t = 65.536 ms, and 32.768 ms for 12 mhz microcontroller clock. the range of intervals is from wdt = 00h. this gives 16.77 ms (for 6 mhz microcontroller clock) or 8.38 ms (for 12 mhz microcontroller clock) to wdt = ffh, which gives 65.536 ms (for 6 mhz microcontroller clock) or 32.768 ms (for 12 mhz microcontroller clock). 15 port alternative functions ports 1, 2 and 3 are shared with alternative functions to enable control of external devices and circuits. these functions are enabled by setting the appropriate sfr and also writing a logic 1 to the port bit that the function occupies. 16 pulse width modulators the device has eight 6-bit pwm outputs for analog control of e.g. volume, balance, bass, treble, brightness, contrast, hue and saturation. the pwm outputs generate pulse patterns with a repetition rate of 21.33 m s, with the high time equal to the pwm sfr value multiplied by 0.33 m s. the analog value is determined by the ratio of the high time to the repetition time. a dc voltage proportional to the pwm setting is obtained by means of an external integration network (low-pass filter). 16.1 pwm control the relevant pwm is enabled by setting the pwm enable bit pwxe in the pwmx control register. the high time is defined by the value pwxv<5:0>. 16.2 tuning pulse width modulator (tpwm) the device has a single 14-bit tpwm that can be used for voltage synthesis tuning. the method of operation is similar to the normal pwm, except that the repetition period is 42.66 m s. 16.2.1 tpwm control two sfrs are used to control the tpwm: tdacl and tdach. the tpwm is enabled by setting bit tpwe in the tdach sfr. the most significant bits td<13:7> alter the high period between 0 and 42.33 m s. the seven least significant bits td<6:0> extend certain pulses by a further 0.33 m s. for example, if td<6:0> = 01h, 1 in 128 periods will be extended by 0.33 m s. if td<6:0> = 02h, 2 in 128 periods will be extended. the tpwm will not start to output a new value until tdach has been written to. therefore, if the value is to be changed, tdacl should be written before tdach. 16.3 software adc (sad) four successive approximation adcs can be implemented in software by using the on-board 8-bit digital-to-analog converter (dac) and analog comparator. 16.3.1 sad control the control of the required analog input is done using channel select bits ch<1:0> in the sad sfr. this selects the required analog input to be passed to one of the inputs of the comparator. the second comparator input is generated by the dac, whose value is set by bits sad<7:0> in the sad and sadb sfrs. a comparison between the two inputs is made when the start compare bit st in the sad sfr is set. this must be at least one instruction cycle after the sad<7:0> value has been set. the result of the comparison is given on vhi one instruction cycle after bit st is set. 16.3.2 sad input voltage the external analog voltage that is used for comparison with the internally generated dac voltage does not have the same voltage range due to the 5 v tolerance of the pin. it is limited to v ddp - v tn where v tn is a maximum of 0.75 v. for further details, refer to the saa55xx and saa56xx software analogue to digital converter application note spg/an99022 . wi 256 wdt C () t = 2000 jun 30 45 philips semiconductors objective speci?cation enhanced tv microcontrollers with on-screen display (osd) saa56xx 16.3.3 sad dc c omparator mode the sad module (see fig.11) incorporates a dc comparator mode, which is selected using the dc_comp control bit in the sadb sfr. this mode enables the microcontroller to detect a threshold crossing at the input to the selected analog input pin (p3.0/adc0, p3.1/adc1, p3.2/adc2 or p3.3/adc3) of the software adc. a level sensitive interrupt is generated when the analog input voltage level at the pin falls below the analog output level of the sad dac. this mode is intended to provide the device with a wake-up mechanism from power-down or idle mode when a key-press on the front panel of the tv is detected. the following software sequence should be used when utilizing this mode for power-down or idle mode: 1. disable int1 using the ie sfr. 2. set int1 to level sensitive using the tcon sfr. 3. set the dac digital input level to the desired threshold level using sad/sadb sfrs and select the required input pin (p3.0, p3.1, p3.2 or p3,3) using ch1 and ch0 in the sad sfr. 4. enter dc compare mode by setting the dc_comp enable bit in the sadb sfr. 5. enable int1 using the ie sfr. 6. enter power-down/idle mode. upon wake-up, the sad should be restored to its conventional operating mode by disabling the dc_comp control bit. handbook, halfpage mbk960 mux 4 : 1 adc0 adc1 adc2 adc3 ch < 1:0 > sad < 3:0 > sadb < 3:0 > v ddp vhi 8-bit dac fig.11 sad block diagram. 17 i 2 c-bus serial i/o the i 2 c-bus consists of a serial data line (sda) and a serial clock line (scl). the definition of the i 2 c-bus protocol can be found in the i 2 c-bus and how to use it (including specification). philips semiconductors . the device operates in four modes: master transmitter master receiver slave transmitter slave receiver. the microcontroller peripheral is controlled by the serial control sfr (s1con) and its status is indicated by the status sfr (s1sta). information is transmitted/received to/from the i 2 c-bus using the data sfr (s1dat). the slave address sfr (s1adr) is used to configure the slave address of the peripheral. the byte level i 2 c-bus serial port is identical to the i 2 c-bus serial port on the p8xc558, except for the clock rate selection bits cr<2:0>. the operation of the subsystem is described in detail in the p8xc558 data sheet. 2000 jun 30 46 philips semiconductors objective speci?cation enhanced tv microcontrollers with on-screen display (osd) saa56xx 17.1 i 2 c-bus modes three different i 2 c-bus selection tables for cr<2:0> can be configured using the rombk sfr (iic_lut<1:0>), as shown in table 16. 17.1.1 n ominal mode (iic_lut<1:0> = 00) this option accommodates the p8xc558 i 2 c-bus, refer to handbook ic20 80c51-based 8-bit microcontrollers . the various serial rates are shown in table 16: table 16 i 2 c-bus serial rates in p8xc558 nominal mode 17.1.2 f ast mode (iic_lut<1:0> = 01) this option accommodates the p8xc558 i 2 c-bus doubled rates, as shown in table 17: table 17 i 2 c-bus serial rates in p8xc558 fast mode 17.1.3 s low mode (iic_lut<1:0> = 10) this option accommodates the p8xc558 i 2 c-bus rates, divided by 2, as shown in table 18: table 18 i 2 c-bus serial rates p8xc558 slow mode remark: in table 16 to table 18, the f clk relates to the clock input of the 80c51 i 2 c-bus module (6 mhz, 12 mhz). 17.2 i 2 c-bus port selection two i 2 c-bus ports are available: scl0/sda0 and scl1/sda1. the ports are selected by using txt21.i 2 c port 0 and txt21.i 2 c port 1. when a port is enabled, any information transmitted from the device goes onto the enabled port. information transmitted to the device can only be acted on if the port is enabled. if both ports are enabled, then data transmitted from the device is seen on both ports. however, data transmitted to the device on one port cannot be seen on the other port. cr2 cr1 cr0 f clk divide by i 2 c-bus bit frequency (khz) at f clk 6 mhz 12 mhz 000 60 100 200 0 0 1 1600 3.75 7.5 0 1 0 40 150 300 0 1 1 30 200 400 1 0 0 240 25 50 1 0 1 3200 1.875 3.75 1 1 0 160 37.5 75 1 1 1 120 50 100 cr2 cr1 cr0 f clk divide by i 2 c-bus bit frequency (khz) at f clk 6 mhz 12 mhz 0 0 0 30 200 400 0 0 1 800 7.5 15 0 1 0 20 300 600 011 15 400 800 1 0 0 120 50 100 1 0 1 1600 3.75 7.5 1 1 0 80 75 150 111 60 100 200 cr2 cr1 cr0 f clk divide by i 2 c-bus bit frequency (khz) at f clk 6 mhz 12 mhz 0 0 0 120 50 100 0 0 1 3200 1.875 3.75 0 1 0 80 75 150 011 60 100 200 1 0 0 480 12.5 25 1 0 1 6400 0.9375 1.875 1 1 0 320 18.75 37.5 1 1 1 240 25 50 2000 jun 30 47 philips semiconductors objective speci?cation enhanced tv microcontrollers with on-screen display (osd) saa56xx 18 uart peripheral the 80c51 microcontroller incorporates a full duplex uart with a single byte receive buffer, meaning that it can commence reception of a second byte before the first is read from the receive buffer. this register is implemented twice. writing to s0buf writes to the transmit buffer. reading from s0buf reads from the receive buffer. only hardware can read from the transmit buffer and write to the receive buffer. the uarts tx and rx pins connect to p0.1 and p0.0, respectively. two registers (s0con, s0buf) and one bit (smod in pcon register) control the uart. table 19 uart special function registers 18.1 uart modes the serial port can operate in four modes: mode 0: serial data enters and exits through rx. tx outputs the shift clock. eight bits are transmitted and received (lsb first). the baud rate is fixed at 1 6 f clk . mode 1: ten bits are transmitted (through tx) or received (through rx): a start bit (logic 0), eight data bits (lsb first) and a stop bit (logic 1). on receive, the stop bit goes into rb8 in sfr s0con. the baud rate can be varied at either timer 1 or timer 2 overflow rate. mode 2: eleven bits are transmitted (through tx) or received (through rx): start bit (logic 0), eight data bits (lsb first), a 9 th data bit and a stop bit (logic 1). on transmit, the 9 th data bit, tb8 in s0con, can be assigned the value of logic 0 or logic 1. for example, the parity bit could be moved into tb8. on receive, the 9 th data bit goes into rb8 in s0con, while the stop bit is ignored. the baud rate can be programmed to either 1 32 f clk or 1 64 f clk . mode 3: eleven bits are transmitted (through tx) or received (through rx): a start bit (logic 0), eight data bits (lsb first), a 9 th data bit and a stop bit (logic 1). in fact, mode 3 is the same as mode 2 in all respects except baud rate. the baud rate can be varied at either timer 1 or timer 2 overflow rate. in all four modes, transmission is initiated by any instruction that uses s0buf as a destination register. reception is initiated in mode 0 by the condition ri = 0 and ren = 1. in the other modes, reception is initiated by the incoming start bit if ren = 1. 18.2 uart multiprocessor communications modes 2 and 3 have a special provision for multiprocessor communications. in these modes, nine data bits are received. the 9 th bit goes into rb8, followed by a stop bit. the port can be programmed such that when the stop bit is received, the serial port interrupt will be activated only if rb8 = 1. this feature is enabled by setting bit sm2 in s0con. a way to use this feature in multiprocessor systems is as follows. when the master processor wants to transmit a block of data to one of several slaves, it first sends out an address byte which identifies the target slave. an address byte differs from a data byte. the 9 th bit is logic 1 in an address byte and logic 0 in a data byte. with sm2 = 1, no slave will be interrupted by a data byte reception. an address byte, however, will interrupt all slaves, so that each slave can examine the received byte and see if it is being addressed. the addressed slave will clear its sm2 bit and prepare to receive the data bytes that will follow. the slaves that were not being addressed leave their sm2 bits set and carry on the task they were performing. bit sm2 has no effect in mode 0; in mode 1, it can be used to check the validity of the stop bit. when receiving in mode 1 (if sm2 = 1), the receive interrupt will not be activated unless a valid stop bit is received. 18.3 s0buf registers this register is implemented twice. writing to s0buf writes to the transmit buffer. reading from s0buf reads from the receive buffer. only hardware can read from the transmit buffer and write to the receive buffer. sfr address s0con 99h s0buf 9ah 2000 jun 30 48 philips semiconductors objective speci?cation enhanced tv microcontrollers with on-screen display (osd) saa56xx 18.4 uart baud rates remark: f clk used in the following calculations refers to the microcontroller clock frequency (6 or 12 mhz). the serial port can operate with different baud rates, depending on its mode. the baud rate in mode 0 is derived from state 2 and state 5, and thus fixed: mode 0 baud rate = 1 6 f clk the baud rate in mode 2 depends on the value of bit smod: if smod = 0, the baud rate is 1 32 f clk if smod = 1, the baud rate is 1 16 f clk mode 2 baud rate = . the baud rates in modes 1 and 3 are determined by the timer overflow rate and the value of smod as follows: modes 1 and 3 baud rate = modes 1 and 3 baud rate = 1 16 timer 2 overflow rate. in this application, the timer 1 interrupt should be disabled. the timer can be configured for either timer or counter operation in any of its three running modes. in the most typical applications, it is configured for timer operation. in the auto-reload mode (high nibble of tmod = 0010b), the baud rate is given by the formula: modes 1 and 3 baud rate = . very low baud rates can be achieved with timer 1 by leaving the timer 1 interrupt enabled and configuring the timer to run as a 16-bit timer (high nibble of tmod = 0001b), plus using the timer 1 interrupt to do a 16-bit software reload. timer 2 has a programming mode to function as baud rate generator for the uart. in this mode, the baud rate is given by the formula: modes 1 and 3 baud rate = . for further details on the uart operation, refer to "handbook ic20 80c51-based 8-bit microcontrollers . 19 led support port pins p0.5 and p0.6 have an 8 ma current sinking capability to enable leds in series with current limiting resistors to be driven directly, without the need for additional buffering circuits. 20 external sram/rom interface the external address/data bus of the 80c51 microprocessor may be interfaced to: additional sram data memory for multi-page acquisition applications external program rom. the application circuit can be achieved using either the multiplexed address and data i/o or the de-multiplexed address and data i/o. it is possible to interface up to 256 kbytes of external data memory using pins rambk<1:0> and a15_bk. each of the four data memory banks is selected by rambk<1:0> (sfr rombk<4:3>), as follows: table 20 rambk selection it is possible to interface up to 192 kbytes of external program rom, which is addressed using the contiguous address bus (a17_ln, a16_ln, a15_ln). remark: although this is an 18-bit bus, the internal microcontroller logic makes it possible to only address 192 bytes with linear addressing. figs. 12 and 13 show the interfacing connections for both external sram data memory and external program memory. 2 smod 32 ----------------- - f clk 2 smod 32 ----------------- - timer 1 overflow rate 2 smod 32 ----------------- - f clk 6 256 t1h C () ------------------------------------------ 1 16 ------ f clk 6 256 t2h C () ------------------------------------------ rambk<1:0> bank external address range 00 bank 0 0 to 64 kbytes 01 bank 1 64 to 128 kbytes 10 bank 2 128 to 192 kbytes 11 bank 3 192 to 256 kbytes 2000 jun 30 49 philips semiconductors objective speci?cation enhanced tv microcontrollers with on-screen display (osd) saa56xx handbook, full pagewidth gsa075 wr we saa56xx sram rd oe rambk < 1 : 0 > a < 17 : 16 > a15_bk a15 a < 14:8 > a < 14:8 > ad < 7:0 > ad < 7:0 > d < 7:0 > a < 7:0 > ale a < 7:0 > ce latch fig.12 external sram configuration. handbook, full pagewidth gsa076 saa56xx rom psen oe rombk<2:0>, a15_bk or a < 17_ln:15_ln > a < 17 : 15 > a < 14:8 > a < 14:8 > ad < 7:0 > ad < 7:0 > d < 7:0 > a < 7:0 > ale a < 7:0 > latch fig.13 external rom configuration. 2000 jun 30 50 philips semiconductors objective speci?cation enhanced tv microcontrollers with on-screen display (osd) saa56xx 21 memory interface the memory interface controls access to the embedded dram, refreshing of the dram and page clearing. the dram is shared between data capture, display and microcontroller sections. the data capture section uses the dram to store acquired information that has been requested. the display reads from the dram information and converts it to rgb values. the microcontroller uses the dram as embedded auxiliary ram. 21.1 memory structure the memory is partitioned into two distinct areas, the dedicated auxiliary ram area and the display ram area. when not being used for data capture or display, the display ram area can be used as an extension to the auxiliary ram area. 21.1.1 a uxiliary ram the auxiliary ram is not initialised at power-up and must be initialised by the application software. its contents are maintained during idle mode and standby mode, but are lost if power-down mode is entered. 21.1.2 d isplay ram the display ram is initialised on power-up to a value of 20h throughout. the contents of the display ram are maintained when entering idle mode. if idle mode is exited using an interrupt, the contents are unchanged, if idle mode is exited using an external reset, the contents are initialised to 20h. full closed caption display requires display ram from 8000h to 845fh. the memory from 8460h to 84ffh (must be initialised by the application software) can be utilised as an extension to the dedicated contiguous auxiliary ram that occupies 0000h to 07ffh. 21.2 memory mapping the dedicated auxiliary ram area occupies 2 kbytes, with an address range from 0000h to 07ffh. the display ram occupies a maximum of 12 kbytes with an address range from 2000h to 5000h for txt mode and 8000h to 84ffh for cc mode (see fig.14). although having different address ranges, the two modes occupy physically the same dram area. 21.3 ccbase sfr the saa56xx incorporates a ccbase sfr, which enables cc display data to be accessed from any 1-kbyte partition within the display memory. this sfr allows the cc base address for closed caption display memory to overlap teletext memory at the following hexadecimal boundaries of the 80c51 microcontroller movx address space: 2000h (same as saa55x default), 2400h, 2800h, 2c00h, 3000h, 3400h, 3800h, 3c00h, 400h0, 4400h, 4800h, 4c00h, 500h0, 5400h, 5800h, 5c00h, 600h0, 6400h, 6800h and 6c00h. the reset value for the ccbase address sfr is 20h, thus ensuring software compatibility with other variants in the saa55xx family. register bits ccbase1 and ccbase0 must always be set to zero at 1-kbyte boundaries. figure 14 shows the default setting for the cc display memory: handbook, halfpage gsa061 upper 32 kbytes lower 32 kbytes auxiliary txt block 0 0000h 0800h 2000h txt block 9 2400h txt block 1 2800h txt block 2 2c00h txt block 3 3000h txt block 4 3400h txt block 5 3800h txt block 6 3c00h txt block 7 4000h txt block 8 txt block 10 txt block 19 4400h 4800h 4c00h 5000h 7fffh cc display 8000h 84ffh ffffh fig.14 dram memory mapping. 2000 jun 30 51 philips semiconductors objective speci?cation enhanced tv microcontrollers with on-screen display (osd) saa56xx 21.4 addressing memory the memory can be addressed by the microcontroller in two ways, either directly using a movx command or via sfrs, depending on what address is required. the dedicated auxiliary ram, and display memory in the range 8000h to 86ffh can only be accessed using the movx command. the display memory in the range 2000h to 47ffh can either be directly accessed using the movx command, or via the sfrs. 21.4.1 txt d isplay memory sfr access when in txt mode (see fig.15), the display memory is configured as 40 columns wide by 25 rows and occupies 1k 8-bit of memory. there can be a maximum of 12 display pages. using txt15.block<3:0> and txt15.micro bank, the required display page can be selected to be written to. the row and column within that block is selected using txt9.r<4:0> and txt10.c<5:0>. the data at the selected position can be read or written using txt11.d<7:0>. whenever a read or write is performed on txt11, the row values stored in txt9 and column value stored in txt10 are automatically incremented. for rows 0 to 24, the column value is incremented up to a maximum of 39, at which point it resets to 0 and increments the row counter value. when row 25 column 23 is reached, the values of the row and column are both reset to 0. writing values outside the valid range for txt9 or txt10 will cause undetermined operation of the auto-incrementing function for accesses to txt11. 21.4.2 txt d isplay memory movx access for the generation of osd displays that use this mode of access, it is important to understand the mapping of the movx address onto the display row and column value. this mapping of row and column onto address is shown in table 21. the values shown are added onto a base address for the required memory block (see fig.15) to give a 16-bit address. table 21 column and row to movx address (lower 10 bits of address in hexadecimal) row col. 0 ..... col. 23 ..... col. 31 col. 32 ..... col. 39 row 0 000 ..... 017 ..... 01f 3f8 ..... 3ff row 1 020 ..... 037 ..... 03f 3f0 ..... 3f7 : ::::: ::: : ::::: ::: row 23 2e0 ..... 3f7 ..... 2ff 340 ..... 347 row 24 300 ..... 317 ..... 31f 338 ..... 33f row 25 320 ..... 337 2000 jun 30 52 philips semiconductors objective speci?cation enhanced tv microcontrollers with on-screen display (osd) saa56xx handbook, full pagewidth 02030 10 c 9 023 39 column 10 mbk962 control data active position txt9.r < 4:0 > = 01h, txt10.c < 5:0 > = 0ah, txt11 = 43h non-displayable data (byte 10 reserved) row 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 fig.15 txt memory map. 2000 jun 30 53 philips semiconductors objective speci?cation enhanced tv microcontrollers with on-screen display (osd) saa56xx 21.5 page clearing page clearing is performed on request from the data capture section or the microcontroller, under the control of the embedded software. at power-on and reset, the whole of the page memory is cleared. bit txt13.page clearing is set while this takes place. 21.5.1 d ata c apture page clear when a page header is acquired for the first time after a new page request or a page header is acquired with the erase (c4) bit set, the page memory is cleared to spaces before the rest of the page arrives. when this occurs, the space code (20h) is written into every location of rows 1 to 23 of the basic page memory, the appropriate packet 27 row of the extension packet memory and the row where teletext packet 24 is written. this last row is either row 24 of the basic page memory (if the txt0.x24 posn bit is set) or row 0 of the extension packet memory (if the bit is not set). page clearing is done before the end of the tv line in which the header arrived which initiated the page clear. this means that the 1 field gap between the page header and the rest of the page which is necessary for many teletext decoders is not required. 21.5.2 s oftware page clear the software can also initiate a page clear by setting bit txt9.clear memory. now, every location in the memory block pointed to by txt15.block<3:0> is cleared to a space code (20h). bit clear memory is not latched, so the software does not have to reset it after it has been set. only one page can be cleared in a tv line. therefore, if the software requests a page clear, it will be carried out on the next tv line on which the data capture hardware does not force the page to be cleared. a flag (txt13.page clearing) is provided to indicate that a software requested page clear is being carried out. the flag is set when a logic 1 is written to bit txt9.clear memory and is reset when the page clear has been completed. all locations are cleared to 00h if bit txt0.inv on = 1 and a page clear is initiated on block 8. 21.6 multi-page operations when using saa56xx in a multi-page application with external sram, bit txt28.multi page should be set. this allows the 80c51 microcontroller to copy acquired data between internal display memory and external sram without hindrance. 2000 jun 30 54 philips semiconductors objective speci?cation enhanced tv microcontrollers with on-screen display (osd) saa56xx 22 data capture the data capture section (see fig.16) takes in the analog composite video and blanking signal (cvbs), and extracts the required data from it in the digital domain. the data is then decoded and stored in memory. the first stage converts the analog cvbs signal to digital form, using adc sampling at 12 mhz. data and clock recovery is then performed by a multi-rate video input processor (mulvip). next, the following types of data are extracted: wst teletext (625/525), vps, closed caption (cc) and wss. the extracted data is stored in either memory (dram) via the memory interface or in sfr locations. 22.1 data capture features two cvbs inputs video signal quality detector data capture for 625-line wst data capture for 525-line wst data capture for line 21 data service (closed caption) data capture for vps data (pdc system a) data capture for wss bit decoding automatic selection between 525 wst/625 wst automatic selection between 625 wst/vps on line 16 of vertical blanking interval (vbi) real-time capture and decoding for wst teletext in hardware, to enable optimized microprocessor throughput up to 12 pages stored on-chip inventory of transmitted teletext pages stored in the transmitted page table and subtitle page table automatic detection of fastext transmission real-time packet 26 engine in hardware for processing accented, g2 and g3 characters signal quality detector for wst/vps data types comprehensive teletext language coverage full field and vbi data capture of wst data. handbook, full pagewidth adc data < 7:0 > vcs sync_filter ttd ttc data slicer and clock recovery output data to memory interface output data to sfrs mbk963 acquisition for wst/vps acquisition for cc/wss cvbs switch cvbs cvbs0 cvbs1 acquisition timing sync separator fig.16 data capture block diagram. 2000 jun 30 55 philips semiconductors objective speci?cation enhanced tv microcontrollers with on-screen display (osd) saa56xx 22.1.1 cvbs s witch the cvbs switch is used to select the required analog input, depending on the value of txt8.cvbs1/ cvbs0. 22.1.2 a nalog - to -d igital c onverter the output of the cvbs switch is passed to a differential-to-single-ended converter (divis, not shown in fig.16), although here it is used in single-ended configuration with a reference. a full-flash adc with a sampling rate of 12 mhz converts the analog output of the divis to a digital representation. 22.1.3 m ulti - rate v ideo i nput p rocessor (m ul vip) the mulvip (used for data and clock recovery) is a digital signal processor designed to extract the data and recover the clock from a digitized cvbs signal. 22.1.4 d ata standards and clock rates the data standards and clock rates that can be recovered are shown in table 22. table 22 data standards and clock rates 22.1.5 d ata c apture timing the data capture timing section uses the synchronisation information extracted from the cvbs signal to generate the required horizontal and vertical reference timings. the timing section automatically recognizes and selects the appropriate timings for either 625 (50 hz) synchronisation or 525 (60 hz) synchronisation. a txt12.video signal quality flag is set when the timing section is locked correctly to the incoming cvbs signal. when txt12.video signal quality is set, another flag txt12.525/ 625 sync can be used to identify the standard. 22.1.6 a cquisition the acquisition section extracts the relevant information from the serial stream of data from the mulvip and stores it in memory. 22.1.6.1 making a page request a page is requested by writing a series of bytes into the txt3.prd<4:0> sfr, which corresponds to the number of the page required. the bytes written into txt3 are stored in a ram with an auto-incrementing address. the start address for the ram is set using the txt2.sc<2:0> (to define which part of the page request is being written) and txt2.req<3:0> (along with txt2.acq bank) is used to define which of the 12 page request blocks is being modified. if txt2.req<3:0> is greater than 09h, then data being written to txt3 is ignored (applies to bank 0 and bank 1). table 23 shows the contents of the page request ram. up to 12 pages of teletext can be acquired on the 12 page device, when txt1.ext pkt off is set to logic 1, and up to 10 pages can be acquired when this bit is set to logic 0. table 23 the contents of the page request ram if the do care bit for part of the page number is set to logic 0, then that part of the page number is ignored when the teletext decoder is deciding whether a page being received off-air should be stored or not. for example, if the do care bits for the four subcode digits are all set to logic 0, then every subcode version of the page will be captured. data standard clock rate 625 wst 6.9375 mhz 525 wst 5.7272 mhz vps 5.0 mhz wss 5.0 mhz closed caption 500 khz start column prd4 prd3 prd2 prd1 prd0 0 do care magazine hold mag2 mag1 mag0 1 do care page tens pt3 pt2 pt1 pt0 2 do care page units pu3 pu2 pu1 pu0 3 do care hour tens x x ht1 ht0 4 do care hours units hu3 hu2 hu1 hu0 5 do care minutes tens x mt2 mt1 mt0 6 do care minutes units mu3 mu2 mu1 mu0 7x xxe1e0 2000 jun 30 56 philips semiconductors objective speci?cation enhanced tv microcontrollers with on-screen display (osd) saa56xx when bit hold is set to a logic 0, the teletext decoder will not recognise any page as having the correct page number and no pages will be captured. in addition to providing the user requested hold function, this bit should be used to prevent the inadvertent capture of an unwanted page when a new page request is being made. for example, if the previous page request was for page 100 and this was being changed to page 234, it would be possible to capture page 200 if this arrived after only the requested magazine number had been changed. bits e1 and e0 control the error checking, which should be carried out on packets 1 to 23 when the page being requested is captured. this is described in more detail in section 22.1.6.3. for a multi-page device, each packet can only be written into one place in the teletext ram. therefore, if a page matches more than one of the page requests, the data is written into the area of memory corresponding to the lowest numbered matching page request. at power-up, each page request defaults to any page, hold on and error check mode 0. 22.1.6.2 rolling headers and time when a new page is requested, it is conventional for the decoder to turn the header row of the display green and to display each page header as it arrives until the correct page is found. when a page request is changed (i.e. when the txt3 sfr is written to), a flag (pblf) is written into bit 5, column 9, row 25 of the corresponding block of the page memory. the state of the flag for each block is updated every tv line 1. if it is set for the current display block, the acquisition section writes all valid page headers that arrive into the display block and automatically writes an alphanumeric green character into column 7 of row 0 of the display block every tv line. when a requested page header is acquired for the first time, rows 1 to 23 of the relevant memory block are cleared to space, i.e. have 20h written into every column, before the rest of the page arrives. row 24 is also cleared if bit txt0.x24 posn is set. if bit txt1.ext pkt off is set, the extension packets corresponding to the page are also cleared. the last eight characters of the page header are used to provide a time display and are always extracted from every valid page header as it arrives and written into the display block. bit txt0.disable header roll prevents any data being written into row 0 of the page memory, except when a page is acquired off-air, i.e. rolling headers and time are not written into the memory. bit txt1.acq off prevents any data being written into the memory by the teletext acquisition section. when a parallel magazine mode transmission is being received, only headers in the magazine of the page requested are considered valid for the purposes of rolling headers and time. only one magazine is used even if the do care magazine bit is set to logic 0. when a serial magazine mode transmission is being received, all page headers are considered to be valid. 22.1.6.3 error checking teletext packets are error checked before they are written into the page memory. the error checking carried out depends on the packet number, the byte number, the error check mode bits in the page request data and bit txt1.8-bit (see fig.17). if an uncorrectable error occurs in one of the hamming checked addressing and control bytes in the page header or in the hamming checked bytes in packet 8/30, bit 4 of the byte written into the memory is set, to act as an error flag to the software. if uncorrectable errors are detected in any other hamming checked data, the byte is not written into the memory. 2000 jun 30 57 philips semiconductors objective speci?cation enhanced tv microcontrollers with on-screen display (osd) saa56xx handbook, full pagewidth mgk465 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 '8-bit' bit = 0 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 '8-bit' bit = 1 packet x/0 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 '8-bit' bit = 0, error check mode = 0 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 '8-bit' bit = 0, error check mode = 1 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 '8-bit' bit = 0, error check mode = 2 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 '8-bit' bit = 0, error check mode = 3 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 '8-bit' bit = 1 packet x/1-23 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 '8-bit' bit = 0 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 '8-bit' bit = 1 packet x/24 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 packet x/27/0 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 packet 8/30/0,1 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 8-bit data packet 8/30/2,3,4-15 odd parity checked 8/4 hamming checked fig.17 error checking. 2000 jun 30 58 philips semiconductors objective speci?cation enhanced tv microcontrollers with on-screen display (osd) saa56xx 22.1.6.4 teletext memory organisation the teletext memory is divided into two banks of ten blocks. normally, when bit txt1.ext pkt off is logic 0, each of blocks 0 to 8 contains a teletext page arranged in the same way as the basic page memory of the page device (see fig.18) and block 9 contains extension packets (applies to bank 0 and bank 1), see fig.19. when bit txt1.ext pkt off is logic 1, no extension packets are captured and block 9 of both bank 0 and bank 1 of the memory are used to store two other pages. the number of the memory block into which a page is written corresponds to the page request number (txt2.req<3:0>) which resulted in the capture of the page. packet 0, the page header, is split into two parts when it is written into the text memory. the first eight bytes of the header contain control and addressing information. they are hamming decoded and written into columns 0 to 7 of row 25, which also contains the magazine number of the acquired page and the pblf flag. however, the last 14 bytes are unused and may be used by the software, if necessary. handbook, full pagewidth row 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 0678 9 023 39 packet x/0 basic page blocks (0 to 9 bank 0; 0 and 9 bank 1) osd only packet x/1 packet x/2 packet x/3 packet x/4 packet x/5 packet x/6 packet x/7 packet x/8 packet x/9 packet x/10 packet x/11 packet x/12 packet x/13 packet x/14 packet x/15 packet x/16 packet x/17 packet x/18 packet x/19 packet x/20 packet x/21 packet x/22 packet x/23 packet x/24 (1) gsa071 control data vps data (2) 10 (3) fig.18 packet storage locations. (1) if x24 posn bit = 1. (2) vps data only in block 9 of either bank 0 or bank 1. (3) byte 10 reserved. 2000 jun 30 59 philips semiconductors objective speci?cation enhanced tv microcontrollers with on-screen display (osd) saa56xx handbook, full pagewidth 0 1 2 3 4 5 6 7 8 9 923 0 10 11 12 13 14 15 20 21 22 23 24 25 16 17 18 19 row packet x/24 for page in block 0 (1) packet x/24 for page in block 1 (1) packet x/27/0 for page in block 0 packet x/27/0 for page in block 1 packet x/24 for page in block 2 (1) packet x/27/0 for page in block 2 packet x/24 for page in block 3 (1) packet x/27/0 for page in block 3 packet x/24 for page in block 4 (1) packet x/27/0 for page in block 4 packet x/24 for page in block 5 (1) packet x/27/0 for page in block 5 packet x/24 for page in block 6 (1) packet x/27/0 for page in block 6 packet x/24 for page in block 7 (1) packet x/27/0 for page in block 7 packet x/24 for page in block 8 (1) packet x/27/0 for page in block 8 packet 8/30/0.1 packet 8/30/2.3 packet 8/30/4-15 packet 8/30/4-15 vps data extension packet (block 9 bank 0) 10 (2) gsa072 0 1 2 3 4 5 6 7 8 9 923 0 10 11 12 13 14 15 20 21 22 23 24 25 16 17 18 19 row packet x/24 for page in block 0 (1) packet x/27/0 for page in block 0 packet 8/30/0.1 packet 8/30/2.3 vps data extension packet (block 9 bank 1) 10 (2) fig.19 extension packet storage locations. (1) if x24 posn bit = 0. (2) byte 10 reserved. 2000 jun 30 60 philips semiconductors objective speci?cation enhanced tv microcontrollers with on-screen display (osd) saa56xx 22.1.6.5 row 25 data contents the hamming error flags are set if the on-board 8/4 hamming checker detects that there has been an uncorrectable (2-bit) error in the associated byte. it is possible for the page to still be acquired if some of the page address information contains uncorrectable errors if that part of the page request was a dont care. there is no error flag for the magazine number because an uncorrectable error in this information prevents the page being acquired. the interrupt sequence (c9) bit is automatically dealt with by the acquisition section, so that rolling headers do not contain a discontinuity in the page number sequence. the magazine serial bit (c11) indicates whether the magazine transmission is serial or parallel. this affects how the acquisition section operates and is dealt with automatically. the newsflash (c5), subtitle (c6), suppress header (c7), inhibit display (c10) and language control (c12 to 14) bits are dealt with automatically by the display section. the update bit (c8) has no effect on the hardware. the remaining 32 bytes of the page header are parity checked and written into columns 8 to 39 of row 0. bytes that pass the parity check have the msb set to a logic 0 and are written into page memory. bytes with parity errors are not written into the memory. table 24 the data in row 25 of the basic page memory col bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0000 hamming error pu3 pu2 pu1 pu0 1000 hamming error pt3 pt2 pt1 pt0 2000 hamming error mu3 mu2 mu1 mu0 3000 hamming error c4 mt2 mt1 mt0 4000 hamming error hu3 hu2 hu1 hu0 5000 hamming error c6 c5 ht1 ht0 6000 hamming error c10 c9 c8 c7 7000 hamming error c14 c13 c12 c11 8000 found 0 mag2 mag1 mag0 9 0 0 pblf 0 0000 10 to 23 --- unused ---- 2000 jun 30 61 philips semiconductors objective speci?cation enhanced tv microcontrollers with on-screen display (osd) saa56xx 22.1.6.6 inventory page if bit txt0.inv on is a logic 1, memory block 8 of bank 0 is used as an inventory page.this consists of two tables: the transmitted page table (tpt) and the subtitle page table (spt); see fig.20. in each table, every possible combination of the page tens and units digit, 00h to ffh, is represented by a byte, see fig.21. each bit of these bytes corresponds to a magazine number so each page number, from 100h to 8ffh, is represented by a bit in the table. the bit for a particular page in the tpt is set when a page header is received for that page. the bit in the spt is set when a page header for the page is received which has the subtitle page header control bit (c6) set. the bit for a particular page in the tpt is set when a page header is received for that page. the bit in the spt is set when a page header for the page is received which has the subtitle page header control bit (c6) set. handbook, full pagewidth mgd165 0 1 2 3 4 5 6 7 8 9 23 0 039 10 11 12 13 14 15 20 21 22 23 24 25 16 17 18 19 row unused unused unused unused unused unused unused unused unused transmitted pages table subtitle pages table fig.20 inventory page organisation. 2000 jun 30 62 philips semiconductors objective speci?cation enhanced tv microcontrollers with on-screen display (osd) saa56xx handbook, full pagewidth x00 x01 x02 x03 x04 x05 x06 x07 x08 x09 x0a x0b x0c x0d x0e x0f x10 x11 x12 x13 x14 x15 x16 x17 x18 x19 x1a x1b x1c x1d x1e x1f x20 x21 x22 x23 x24 x25 x26 x27 x28 x29 x2a x2b x2c x2d x2e x2f x30 x31 x32 x33 x34 x35 x36 x37 x38 x39 x3a x3b x3c x3d x3e x3f xc0 xc1 xc2 xc3 xc4 xc5 xc6 xc7 xc8 xc9 xca xcb xcc xcd xce xcf xd0 xd1 xd2 xd3 xd4 xd5 xd6 xd7 xd8 xd9 xda xdb xdc xdd xde xdf xe0 xe1 xe2 xe3 xe4 xe5 xe6 xe7 xe8 xe9 xea xeb xec xed xee xfef xf0 xf1 xf2 xf3 xf4 xf5 xf6 xf7 xf8 xf9 xfa xfb xfc xfd xfe xff 7xx bit 7 bytes in the table bits in each byte column row n n + 1 n + 6 n + 7 0 0 mgd160 81624 3239 6xx 5xx 4xx 3xx 2xx 1xx 8xx fig.21 transmitted/subtitle page organisation. 22.1.6.7 packet 26 processing one of the uses of packet 26 is to transmit characters that are not in the basic teletext character set. the family automatically decodes packet 26 data and, if a character corresponding to that being transmitted is available in the character set, automatically writes the appropriate character code into the correct location in the teletext memory. this is not a full implementation of the packet 26 specification allowed for in level 2 teletext, and so is often referred to as level 1.5. by convention, the packets 26 for a page are transmitted before the normal packets. to prevent the default character data overwriting the packet 26 data, there is a mechanism which prevents packet 26 data from being overwritten. the mechanism is disabled when the spanish national option is detected because the spanish transmission system sends even parity (i.e. incorrect) characters in the basic page locations corresponding to the characters sent via packet 26 and these will not overwrite the packet 26 characters anyway. the special treatment of the spanish national option is disabled if bit txt12.spanish is cleared (logic 0) or if bit txt8.disable spanish is set (logic 1). packet 26 data is processed regardless of bit txt1.ext pkt off, but setting bit txt1.x26 off disables packet 26 processing. bit txt8.pkt26 received is set by the hardware whenever the packet 26 decoding hardware writes a character into the page memory. the flag can be reset by writing a logic 0 into the sfr bit. 22.1.6.8 525-line world system teletext the 525-line format (see fig.22) is similar to the 625-line format but the data rate is lower and there are fewer data bytes per packet (32 rather than 40). there are still 40 characters per display row so extra packets are sent, each containing the last eight characters for four rows. these packets can be identified by the tabulation bit (t), which replaces one of the magazine bits in 525-line teletext. when an ordinary packet with t = 1 is received, the decoder puts the data into the four rows, starting with that corresponding to the packet number, but with the two lsbs set to logic 0. for example, a packet 9 with t = 1 (packet x/1/9) contains data for rows 8, 9, 10 and 11. the error checking carried out on data from packets with t = 1 depends on the setting of bit txt1.8-bit and the error checking control bits in the page request data and is the same as that applied to the data written into the same memory location in the 625-line format. the rolling time display (the last eight characters in row 0) is taken from any packets x/1/1, 2 or 3 received. in parallel magazine mode, only packets in the correct magazine are used for the rolling time. packet number x/1/0 is ignored. 2000 jun 30 63 philips semiconductors objective speci?cation enhanced tv microcontrollers with on-screen display (osd) saa56xx the tabulation bit is also used with extension packets. the first eight data bytes of packet x/1/24 are used to extend the fastext prompt row to 40 characters. these characters are written into whichever part of the memory the packet 24 is being written into (determined by the x24 posn bit). packets x/0/27/0 contain five fastext page links and the link control byte. they are captured, hamming checked and stored in the same way as are packets x/27/0 in 625-line text. packets x/1/27/0 are not captured. because there are only two magazine bits in 525-line text, packets with the magazine bits all set to a logic 0 are referred to as being in magazine 4. therefore, the broadcast service data packet is packet 4/30, rather than packet 8/30. as in 625-line text, the first 20 bytes of packet 4/30 contain encoded data that is decoded in the same way as in packet 8/30. the last 12 bytes of the packet contains half of the parity encoded status message. packet 4/0/30 contains the first half of the message and packet 4/1/30 contains the second half. the last four bytes of the message are not written into memory. the first 20 bytes of the each version of the packet are the same, so they are stored whenever either version of the packet is acquired. in 525-line text, each packet 26 only contains ten 24/18 hamming encoded data triplets, rather than the 13 found in 625-line text. the tabulation bit is used as an extra bit (the msb) of the designation code, allowing 32 packet 26s to be transmitted for each page. the last byte of each packet 26 is ignored. handbook, full pagewidth gsa004 row 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 0678 9 023 39 packet x/0/0 osd only rolling time aw/ag packet x/0/1 packet x/1/1 packet x/0/2 packet x/0/3 packet x/0/4 packet x/1/4 packet x/0/5 packet x/0/6 packet x/0/7 packet x/0/8 packet x/1/8 packet x/0/9 packet x/0/10 packet x/0/11 packet x/0/12 packet x/1/12 packet x/0/13 packet x/0/14 packet x/0/15 packet x/0/16 packet x/1/16 packet x/0/17 packet x/0/18 packet x/0/19 packet x/0/20 packet x/1/20 packet x/0/21 packet x/0/22 packet x/0/23 packet x/0/24 (1) packet x/1 /24 (1) control data 10 (2) fig.22 packet storage locations, 525-line. (1) if x24 posn bit = 1. (2) byte 10 reserved. 2000 jun 30 64 philips semiconductors objective speci?cation enhanced tv microcontrollers with on-screen display (osd) saa56xx 22.1.6.9 fastext detection when a packet 27, designation code 0 is detected, whether or not it is acquired, bit txt13.fastext is set. if the device is receiving 525-line teletext, a packet x/0/27/0 is required to set the flag. the flag can be reset by writing a logic 0 into the sfr bit. when a packet 8/30 is detected (or a packet 4/30 when the device is receiving a 525-line transmission), flag txt13.pkt 8/30 is set. the flag can be reset by writing a logic 0 into the sfr bit. 22.1.6.10 broadcast service data detection when a packet 8/30 is detected (or a packet 4/30 when the device is receiving a 525-line transmission), flag txt13. pkt 8/30 is set. the flag can be reset by writing a logic 0 into the sfr bit. 22.1.6.11 vps acquisition when bit txt0.vps on is set, any vps data present on line 16, field 0 of the cvbs signal at the input of the teletext decoder is error checked and stored in row 25, block 9 of the basic page memory, see fig.23. the device automatically detects whether teletext or vps is being transmitted on this line and decodes the data appropriately. each vps byte in the memory consists of four biphase decoded data bits (bits 0 to 3), a biphase error flag (bit 4) and three logic 0s (bits 5 to 7). the most significant bit of the vps data cannot be set to logic 1. bit txt13.vps received is set by the hardware whenever vps data is acquired. full details of the vps system can be found in the specification domestic video program delivery control system (pdc); ebu tech. 3262-e. 22.1.7 wst acquisition the saa56xx family is capable of acquiring level 1.5 625-line and 525-line world system teletext. 22.1.8 wss acquisition the wss data transmitted on line 23 gives information on the aspect ratio and display position of the transmitted picture, the position of subtitles and on the camera/film mode. some additional bits are reserved for future use. a total of 14 data bits are transmitted. all of the available data bits transmitted by the wss signal are captured and stored in sfrs wss1, wss2 and wss3. the bits are stored as groups of related bits and an error flag is provided for each group to indicate when a transmission error has been detected in one or more of the bits in the group. wss data is only acquired when the txt8.wss on bit is set. bit txt8.wss received is set by the hardware whenever wss data is acquired. the flag can be reset by writing a logic 0 into the sfr bit. 22.1.9 c losed c aption acquisition the us closed caption data is transmitted on line 21 (525-line timings) and is used for captioning information, text information and extended data services. full details can be found in the document recommended practise for line 21 data service eia-608 . closed caption data is only acquired when bit txt21.cc on is set. two bytes of data are stored per field in sfrs. the first byte is stored in ccdat1 and the second byte is stored in ccdat2. the value in the ccdat registers is reset to 00h at the start of the closed caption line defined by cclin.cs<4:0>. at the end of the closed caption line, an interrupt is generated if ie.ecc is active. the closed caption data is software-processed to convert it into a displayable format. handbook, full pagewidth teletext page header data vps byte 11 row 25 10 11 column 0 9 mbk964 vps byte 12 vps byte 13 vps byte 14 vps byte 15 vps byte 4 vps byte 5 12 13 14 15 16 17 18 19 20 21 22 23 fig.23 vps data storage. 2000 jun 30 65 philips semiconductors objective speci?cation enhanced tv microcontrollers with on-screen display (osd) saa56xx 23 display the display section (see fig.24) is based on the requirements for a level 1.5 wst teletext and us closed caption. there are some enhancements for use with locally generated on-screen displays. the display section reads the contents of the display memory and interprets the control/character codes. from this information and other global settings, the display produces the required rgb signals and video/data (fast blanking) signal for a tv signal processing device. the display is synchronized to the tv signal processing device by horizontal and vertical sync signals from external circuits (slave sync mode). all display timings are derived from these signals. the saa56xx display section incorporates a number of enhancements over the rest of the saa55xx family, including 100 hz (2h/2v only) operation, two page mode primarily for 16:9 screens (50 hz only), increased drcs/special graphics and a larger character rom. handbook, full pagewidth microprocessor interface display timing hsync vsync character font addressing address data data address address data data address data control to memory interface from memory interface phase selector function registers for page a and page b page b parallel/serial converter with smoothing and fringing attribute handling for page a and page b clut ram display data addressing for page a and page b gsa062 clk 12/24 mhz display character rom and drcs data buffer dac dac dac gbfb r fig.24 display block diagram. 2000 jun 30 66 philips semiconductors objective speci?cation enhanced tv microcontrollers with on-screen display (osd) saa56xx 23.1 display features teletext and enhanced osd modes level 1.5 wst features us closed caption features 50/60 hz or 100/120 hz display timing modes two page operation (50 hz only) serial and parallel display attributes single/double/quadruple width and height for characters smoothing capability of double size, double width, double height and quadruple size characters scrolling of display region variable flash rate controlled by software globally selectable scan lines per row 9/10/13/16 globally selectable character matrix (h v) 12 9, 12 10, 12 13, 12 16 italics soft colours using clut with 4096 colour palette underline overline fringing (shadow) selectable from n-s-e-w direction fringe colour selectable meshing of defined area contrast reduction of defined area (both cc and teletext display modes cursor special graphics characters with two planes, allowing four colours per character 64 software redefinable osd characters up to 4 wst character sets (g0/g2) user programmable in a single device (e.g. latin, cyrillic, greek and arabic) g1 mosaic graphics, limited g3 line drawing characters wst character sets and closed caption character set user programmable in a single device. 23.2 display modes the display section has two distinct modes with different features available in each: txt: this is the wst mode with additional serial and global attributes. a txt window is configured as a fixed 25 rows with 40 characters per row. cc: this is the us closed caption mode. a cc window is configured as a maximum of 16 rows with a maximum of 48 characters per row. in both of the above modes, the character matrix and tv lines per row can be defined. there is an option of a character matrix (h v) of 12 9, 12 10, 12 13, or 12 16, and 9, 10, 13 and 16 tv lines per display row. not all combinations of tv lines per row and maximum display rows give a sensible osd display, since there is a limited number of tv scan lines available. sfr txt21 and memory mapped registers are used to control the mode selection. the features will now be described and their function in each of the modes given. if the feature is different in either mode then this is stated. 2000 jun 30 67 philips semiconductors objective speci?cation enhanced tv microcontrollers with on-screen display (osd) saa56xx 23.2.1 f eatures available and characters in each mode table 25 shows a list of features available in each mode, and also if the setting is a serial/parallel attribute, or has a global effect on all the display. table 25 display features and characters in each mode feature txt cc flash serial serial boxes txt/osd (serial) serial horizontal size 1, 2 or 4 (serial) 1 or 2 (serial) vertical size 1 or 2 (serial); 4 (global) 1 or 2 (serial) italic n/a serial foreground colours 8 (serial) 8 + 8 (parallel) background colours 8 (serial) 16 (serial) soft colours (clut) 16 from 4096 16 from 4096 underline n/a serial overline n/a serial fringe n + s+e+w n+s+e+w fringe colour 16 (global) 16 (serial) meshing of background black or colour (global) all (global) fast blanking polarity yes yes screen colour 16 (global) 16 (global) drcs 64 (global) 64 (global) character matrix (h v) 12 9, 12 10, 12 13 or 12 16 12 9, 12 10, 12 13 or 12 16 number of rows 25 16 number of columns 40 48 number of characters displayable 1000 768 cursor yes yes special graphics (2 planes per character) 32 32 (default), 128 if extended special graphics on scroll no yes smoothing yes (global) yes (global) contrast reduction yes (global) yes (serial) 2000 jun 30 68 philips semiconductors objective speci?cation enhanced tv microcontrollers with on-screen display (osd) saa56xx 23.3 display timing modes the display can be configured for either 50/60 hz or 100/120 hz (2h/2v only) using the display configuration mmr 87ffh. table 26 display timing modes display timing (mmr 87ffh) supported hsync/vsync rate display clock number of characters 100 hz bit two_page bit 0 0 1h/1v 12 mhz 40 (single window) 0 1 1h/1v 24 mhz 80 (double window) 1 0 1h/1v; 2h/2v 24 mhz 40 (single window) 1 1 1h/1v 24 mhz 80 (double window) 23.3.1 d ouble window operation this mode enables two different pages to be displayed side by side for use with 16:9 tv screens. the display section clock runs at 24 mhz in this mode. fig.25 shows the combination of two page display possible on the saa56xx device. two page mode is selected using mmr 87ffh bit 0. the two pages displayed are separated by two character spaces to allow the display logic to switch correctly from one window to the other. the facility is restricted to 1h/1v (i.e. 50/60hz display tvs). two control bits exist in double window mode to select closed caption display or text display in each window: txt21.cc/txt for page a and txt28.cc_txt b for page b. txt: when displaying two teletext pages side by side, the memory block being displayed in page a is selected using sfr txt14<3:0> and for page b using sfr txt28<3:0>. the data capture section writes the header and time information only to the memory block corresponding to the active page. this active page is determined with the txt28.active page bit. when set to logic 0, page a is active, set to logic 1, page b is active. operation of the reveal bit (txt7.5) and cursor on bit (txt7.6) only affects the active page. cc: when cc display mode is selected in two page mode, only one window may be used for cc/osd and the other either text or video. two page cc display side by side is not possible. 23.3.2 s ingle window operation at reset, the device defaults to single window mode, which corresponds to 87ffh bit 0 set to logic 0. in this mode, the settings applying to the window displayed are those that would apply to page a in double window mode. for 2h/2v display tvs, the 100 hz bit, mmr 87ffh bit 1, must be set to logic 1 to fit a whole display window. for 1h/1v display tvs, when mmr 87ffh bit 1 is set to logic 0, the display window occupies the whole screen, whereas if mmr 87ffh bit 1 is set to logic 1, only half the screen would be occupied by the display window. this latter configuration would give the same kind of display as in the double window mode with page a: cc or text page b: video. 2000 jun 30 69 philips semiconductors objective speci?cation enhanced tv microcontrollers with on-screen display (osd) saa56xx o k, full pagewidth gsa077 cc osd page a screen colour area text page b page a screen colour area text page b cc osd page a screen colour area cc page b page a screen colour area video video page b cc osd page a screen colour area video text page b page a screen colour area text text page b page a screen colour area text page b text osd page a screen colour area text page b text subtitle video page a text osd page b screen colour area cc page a video page b screen colour area text subtitle page a text page b screen colour area text osd page a video page b screen colour area cc osd page a video page b screen colour area page a screen colour area text osd page b text osd fig.25 two-page text/cc/video combinations. 2000 jun 30 70 philips semiconductors objective speci?cation enhanced tv microcontrollers with on-screen display (osd) saa56xx 23.4 display feature descriptions all display features are now described in detail for both txt and cc modes. 23.4.1 f lash flashing causes the foreground colour pixels to be displayed as the background pixels. the flash frequency is controlled by software setting and resetting the mmr status (see table 40) at the appropriate interval. cc: this attribute is valid from the time set (see table 32) until the end of the row of a display window, or until otherwise modified. txt: this attribute is set by the control character flash (08h) (see fig.34) and remains valid until the end of a row of a display window, or until reset by the control character steady (09h). 23.4.2 b oxes cc: this attribute is valid from the time set until the end of a row of a display window, or otherwise modified if set with serial mode 0. if set with serial mode 1, then it is set from the next character onwards. in text mode (within cc mode), the background colour is displayed regardless of the setting of the box attribute bit. boxes take effect only during mixed mode. where boxes are set in this mode, the background colour is displayed. character locations where boxes are not set show video/screen colour (depending on the setting in the mmr display control) instead of the background colour. txt: two types of boxes exist: the teletext box and the osd box. the teletext box is activated by the start box control character (0bh), two start box characters are required to begin a teletext box, with the box starting between the two characters. the box ends at the end of the line or after an end box control character. txt mode can also use osd boxes, which are started using size implying osd control characters (bch/bdh/beh/bfh). the box starts after the control character (set after) and ends either at the end of a row of a display window, or at the next size implying osd character (set at). the attributes flash, teletext box, conceal, separate graphics, twist and hold graphics are all reset at the start of an osd box, as they are at the start of the row. osd boxes are only valid in tv mode, which is defined by txt5 = 03h and txt6 = 03h. 23.4.3 s ize the size of the characters can be modified in both the horizontal and vertical directions. cc: two sizes are available in both the horizontal and vertical directions. the sizes available are normal ( 1), double ( 2) height/width and any combination of these. the attribute setting is always valid for the whole row of a display window. mixing of sizes within a row is not possible. txt: three horizontal sizes are available: normal ( 1), double ( 2), quadruple ( 4). the control characters normal size (0ch/bch) enable normal size. the double width or double size (0eh/beh/0fh/bfh) control characters enable double width characters. any two consecutive combinations of double width or double size (0eh/beh/0fh/bfh) control characters activate quadruple width characters, provided quadruple width characters are enabled by txt4.quad width enable. three vertical sizes are available normal ( 1), double ( 2) and quadruple ( 4). the control characters normal size (0ch/bch) enable normal size, the double height or double size (0dh/bdh/0fh/bfh) enable double height characters. quadruple height characters are achieved by using double height characters and setting the global attributes txt7.double height (expand) and txt7.bottom/ top. if double height characters are used in teletext mode, single height characters in the lower row of the double height character are automatically disabled. 23.4.4 i talic cc: this attribute is valid from the time set until the end of a row of a display window, or otherwise modified. the attribute causes the character foreground pixels to be offset horizontally by 1 pixel per 4 scan lines (interlaced mode). the base is the bottom left character matrix pixel. the pattern of the character is indented, as shown in fig.26. txt: the italic attribute is not available. 2000 jun 30 71 philips semiconductors objective speci?cation enhanced tv microcontrollers with on-screen display (osd) saa56xx handbook, full pagewidth 0 0 1 3 5 7 8 9 10 field 1 12 16 character matrix 12 13 character matrix indented by 7/6/4 indented by 6/5/3 indented by 5/4/2 indented by 4/3/1 indented by 3/2/0 indented by 2/1 indented by 1/0 mbk970 field 2 11 12 13 14 15 2 2 4 4 6 6 810 0 2 4 6 810 indented by 0 02468100246810 12 10 character matrix 02468100246810 fig.26 italic characters. 23.4.5 c olours a colour look-up table (clut) with 16 colour entries is provided. the colours can be programmed from a palette of 4096 (4 bits per r, g and b), as shown in table 27. the clut is defined by writing data to a ram that resides in the movx address space of the 80c51. when set, the colours are global and apply to all display windows. table 27 clut colour values 23.4.6 f oreground c olour cc: the foreground colour can be chosen from eight colours on a character by character basis. two sets of eight colours are provided. a serial attribute switches between the banks (see table 32 serial mode 1, bit 7). the colours are the clut entries 0 to 7 or 8 to 15. txt: the foreground colour is selected via a control character (see fig.32). the colour control characters takes effect at the start of the next character (set after) and remain valid until the end of a row of a display window, or until modified by a control character. only eight foreground colours are available. the text foreground control characters map to the clut entries, as shown in table 28. table 28 foreground clut mapping red<3:0> (b11 to b8) green<3:0 > (b7 to b4) blue<3:0> (b3 to b0) colour entry 0000 0000 0000 0 0000 0000 1111 1 ... ... ... ... 1111 1111 0000 14 1111 1111 1111 15 control code defined colour clut entry 00h black 0 01h red 1 02h green 2 03h yellow 3 04h blue 4 05h magenta 5 06h cyan 6 07h white 7 2000 jun 30 72 philips semiconductors objective speci?cation enhanced tv microcontrollers with on-screen display (osd) saa56xx 23.4.7 b ackground colour cc: this attribute is valid from the time set until the end of a row of a display window, or otherwise modified if set with serial mode 0. if set with serial mode 1, then the colour is set from the next character onwards. the background colour can be chosen from all 16 clut entries. txt: the control character new background (1dh) is used to change the background colour to the current foreground colour. the selection is immediate (set at) and remains valid until the end of a row of a display window, or until otherwise modified. the text background control characters map to the clut entries, as shown in table 29. table 29 background clut mapping 23.4.8 b ackground duration when set, the attribute takes effect from the current position until the end of the display window. this is defined in the mmr text area end in single window mode and in double window mode for page a, with mmr text area end b for page b. cc: the background duration attribute (see table 32, bit 8) in combination with the end of row attribute (see table 32, bit 9) forces the background colour to be displayed on the row until the end of the text area is reached. txt: this attribute is not available. 23.4.9 u nderline the underline attribute causes the characters to have the bottom scan line of the character cell forced to foreground colour, including spaces. if background duration is set, then underline is set until the end of the display window. cc: the underline attribute (see table 32, bit 4) is valid from the time set until the end of row of a display window, or otherwise modified. txt: this attribute is not available. 23.4.10 o verline the overline attribute causes the characters to have the top scan line of the character cell forced to foreground colour, including spaces. if background duration is set, then overline is set until the end of the display window. cc: the overline attribute (see table 32, bit 5) is valid from the time set until the end of a row of a display window, or otherwise modified. overlining of italic characters is not possible. txt: this attribute is not available. 23.4.11 e nd of r ow cc: the number of characters in a row is flexible and can be determined by the end of row attribute (see table 32, bit 9). however, the maximum number of character positions displayed is determined by the setting of the mmr text area start or text area start b, and mmr text area end or text area end b. note that, when using the end of row attribute, the next character location after the attribute should always be occupied by a space. txt: this attribute is not available, the row length is fixed at 40 characters. control code defined colour clut entry 00h + 1dh black 8 01h + 1dh red 9 02h + 1dh green 10 03h + 1dh yellow 11 04h + 1dh blue 12 05h + 1dh magenta 13 06h + 1dh cyan 14 07h + 1dh white 15 2000 jun 30 73 philips semiconductors objective speci?cation enhanced tv microcontrollers with on-screen display (osd) saa56xx 23.4.12 f ringing a fringe (shadow) can be defined around characters. the fringe direction is individually selectable in any of the north, south, east and west directions using the mmr fringing control. the colour of the fringe can also be defined as one of the entries in the clut, again using mmr fringing control. an example of fringing is shown in fig.27. cc: the fringe attribute (see table 32, bit 9) is valid from the time set until the end of a row of a display window, or otherwise modified. txt: bit txt4.shadow enable controls the display of fringing in single page mode and in double page a. bit txt26.shadow enable b controls the display of fringing for page b in double window mode. when set, all the alphanumeric characters being displayed are shadowed, graphics characters are not shadowed. handbook, full pagewidth mbk972 fig.27 south and south-west fringing. 23.4.13 m eshing this attribute affects the background colour being displayed. alternate pixels are displayed as the background colour or video. the structure is offset by one pixel from scan line to scan line, thus achieving a checker board display of the background colour and video. an example of meshing and meshing/fringing is shown in fig.28. cc: the setting of the msh bit in mmr display control has the effect of meshing any background colour. txt: there are two meshing attributes. one only affects black background colours txt4.b mesh enable in single window mode or in double window mode for page a, and txt26.b mesh enable b for page b. a second only affects backgrounds other than black txt4.c mesh enable in single window mode or in double window mode for page a, and txt26.c mesh enable b for page b. a black background is defined as clut entry 8, a non-black background is defined as clut entry 9 to 15. 2000 jun 30 74 philips semiconductors objective speci?cation enhanced tv microcontrollers with on-screen display (osd) saa56xx handbook, full pagewidth mbk973 fig.28 meshing and meshing/fringing (south + west). fig.28 meshing and meshing/fringing (south + west). 23.4.14 c ursor the cursor operates by reversing the background (see fig.29) and foreground colours in the character position pointed to by the current cursor position in the active page. the cursor is enabled using txt7.cursor on. when set, the row on which the cursor appears is defined by txt9.r<4:0>; the column is defined by txt10.c<5:0>. the active page is defined by txt28.active page in double window mode and the displayed window is in single window mode. the position of the cursor can be fixed using txt9.cursor freeze. cc: the valid range for row is 0 to 15. the valid range for column is 0 to 47. the cursor remains rectangular at all times, its shape is not affected by italic attribute, therefore it is not advised to use the cursor with italic characters. txt: the valid range for row positioning is 0 to 24. the valid range for column is 0 to 39. handbook, full pagewidth mbk971 ab c def fig.29 cursor display. 2000 jun 30 75 philips semiconductors objective speci?cation enhanced tv microcontrollers with on-screen display (osd) saa56xx 23.4.15 d ynamically r edefinable c haracters (drc s ) a number of drcs are available (see fig.30). these are mapped onto the normal character codes, and replace the predefined character rom value. by default there are 32 drcs occupying the character codes 80h to 8fh. the saa56xx family of devices offers 32 additional drcs over the saa55xx by setting txt267. the first 16 of them occupy the character codes a0 to af, the second 16 occupy the character codes c0 to cf. the remapping of the standard osd to the drcs is activated when the txt20.drcs enable bit for single page mode or for page a in double window mode, and txt23.drcs b enable for page b in double window mode. each character is stored in a matrix of 12 16 1 (v h planes), this allows for all possible character matrices to be defined within a single location. handbook, full pagewidth gsa063 character 46 character 0 address (hex) aeh 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f character 48 c0h character 49 c1h character 47 afh character 62 ceh character 63 12 bits cfh character 30 9eh character 32 a0h character 33 a1h 8bc0 8bdf character 31 9fh 8be0 additional drcs for txt26.7 = 1 8bff character 0 address (hex) character code 80h character 1 81h character 2 82h 8800 881f 8820 883f 8840 885f fig.30 organisation of drc ram the saa56xx family of devices offers 32 additional drcs over the saa55xx by setting txt26.7. the first 16 of them occupy character codes a0 to af, the second 16 occupy character codes c0 to cf. 2000 jun 30 76 philips semiconductors objective speci?cation enhanced tv microcontrollers with on-screen display (osd) saa56xx 23.4.16 d efining characters the drc ram is mapped into the 80c51 ram address space and starts at location 8800h. the character matrix is 12 bits wide and therefore requires two bytes to be written for each word. the first byte (even addresses), addresses the lower eight bits and the lower nibble of the second byte (odd addresses) addresses the upper four bits. for characters of 9, 10 or 16 lines high, the pixel information starts in the first address and continues sequentially for the required number of addresses. characters of 13 lines high are defined with an initial offset of one address, to allow for the correct generation of fringing across boundaries of clustered characters (see fig.31). the characters continue sequentially for 13 lines, after which a further line can again be used for the generation of correct fringing across boundaries of clustered characters. 23.4.17 s pecial graphics characters several special graphics characters (see fig.32 for an example) are provided for improved osd effects, to provide a choice of four colours within a character cell, see table 30. table 30 special graphics character colour allocation by default, the colours are stored in the character rom location of character codes 8xh and 9xh of the character table (32 rom characters), or in the drcs ram. if txt26.extended drcs is set, the colours are stored in character codes 8xh, 9xh, axh and cxh, or in the drcs ram, including the extended location (64 characters). each special graphics character uses two consecutive normal characters. osd/txt: the saa56xx family of devices allow for 16 special graphics characters if txt26.extended drcs = 0 and 32 if txt26.extended drcs = 1. the double plane decoding for the special graphics is set by txt20.osd planes in single window mode or for page a in double window mode, or by setting txt29.osd planes b for page b in double window mode. osd/cc: for txt20.5 = 0, the conditions are the same as in osd/txt mode. for txt20.5 = 1, any character location can be used as special graphics using bit 14 of its parallel code (see table 31), extended special graphic attributes. remark: fringing, underline, overline and smoothing are not possible for special graphics. if the screen colour is transparent (implicit in mixed mode) and the box attribute is set inside the object, the object is surrounded by video. if the box attribute is not set, the background colour inside the object will also be displayed as transparent. handbook, halfpage line 13 from character above line 1 from character below top left pixel msb lsb mbk975 hex 440 003 00c 030 0c0 300 c00 c00 300 0c0 030 00c 003 000 1a8 000 line number 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 fringing top line bottom right pixel bottom line fringing line not used fig.31 13-line high drcs character format. plane 1 plane 0 colour allocation 0 0 background colour 0 1 foreground colour 1 0 clut entry 6 1 1 clut entry 7 2000 jun 30 77 philips semiconductors objective speci?cation enhanced tv microcontrollers with on-screen display (osd) saa56xx handbook, full pagewidth mgk550 volume background colour "set at" (mode 0) background colour "set after" (mode 1) serial attribute foreground colour 7 background colour special character foreground colour normal character foreground colour 6 fig.32 example of a special graphics character. this example could also be done with 8 special characters. 2000 jun 30 78 philips semiconductors objective speci?cation enhanced tv microcontrollers with on-screen display (osd) saa56xx 23.4.18 s moothing to improve the appearance of the display, the saa56xx family of devices incorporates a smoothing algorithm to insert extra pixels for all character sizes other than normal size (see fig.33). smoothing is available in both txt and cc modes. mmr 87e4h bit 4 enables smoothing in single page mode and for page a in double window mode. mmr 87e4h bit 5 enables smoothing for page b in double window mode. the appearance of special graphics characters and fringed characters cannot be improved with the smoothing algorithm. handbook, full pagewidth gsa078 normal size double width smoothing on double size smoothing on double height smoothing on double width smoothing off double size smoothing off double height smoothing off fig.33 smoothing characters. 2000 jun 30 79 philips semiconductors objective speci?cation enhanced tv microcontrollers with on-screen display (osd) saa56xx 23.4.19 contrast reduction the device can act on the tvs display circuit to reduce contrast of the video by driving the cor output low. contrast reduction improves the readability of characters in mixed mode. txt: bits cor in in sfrs txt5 and txt6 control when the cor output of the device is activated. these bits allow, for example, the display to be set up so that the areas inside teletext boxes are contrast reduced when a subtitle is displayed, leaving the rest of the screen displayed as in normal conditions. cc: here, the contrast reduction is controlled by the contrast reduction attribute (see table 32). this attribute is valid from the time set until the end of a row of a display window, or otherwise modified if set with serial mode 0. if set with serial mode 1, it is set from the next character onwards. 23.5 character and attribute coding this section describes the character and attribute coding for each mode. 23.5.1 cc mode character coding is split into character oriented attributes (parallel, see table 31) and character group coding (serial, see table 32). the serial attributes take effect either at the position of the attribute (set at), or at the following location (set after) and remain effective until either modified by a new serial attribute or until the end of a row of a display window. a serial attribute is represented as a space (the space character itself however is not used for this purpose). the attributes that are still active, e.g. overline and underline, are visible during the display of the space. the default setting at the start of a row is: 1 size flash off overline off underline off italics off display mode = superimpose fringing off background colour duration = 0 end of row = 0. the coding is done in 15-bit words. the codes are stored sequentially in the display memory. a maximum of 768 character positions can be defined for a single display. 23.5.2 txt mode character coding is in a serial format, with only one attribute being changed at any single location. the serial attributes take effect either at the position of the attribute (set at), or at the following location (set after). the attribute remains effective until either modified by new serial attributes or until the end of a row of a display window. the default settings at the start of a row are: foreground colour white (clut address 7) background colour black (clut address 8) horizontal size 1, vertical size 1 (normal size) alphanumeric on contiguous mosaic graphics release mosaics flash off box off conceal off twist off. the attributes have individual codes which are defined in the basic character table (see fig.34). 23.5.3 p arallel character coding table 31 parallel character coding bits description 0 to 7 8-bit character code 8 to 10 three bits for eight foreground colours 11 mode bit: 0 = parallel code 12 to 13 character set selection 14 special graphics 2000 jun 30 80 philips semiconductors objective speci?cation enhanced tv microcontrollers with on-screen display (osd) saa56xx 23.5.4 s erial c haracter c oding table 32 serial character coding bits description serial mode 0 (set at) serial mode 1 char.pos. 1 (set at) char.pos. >1 (set after) 0 to 3 4 bits for 16 background colours 4 bits for 16 background colours 4 bits for 16 background colours 4 underline switch: horizontal size: underline switch: 0 = underline off 0 = normal 0 = underline off 1 = underline on 1 = 2 1 = underline on 5 overline switch: vertical size: overline switch: 0 = overline off 0 = normal 0 = overline off 1 = overline on 1 = 2 1 = overline on 6 display mode: display mode: display mode: 0 = superimpose 0 = superimpose 0 = superimpose 1 = boxing 1 = boxing 1 = boxing 7 flash switch: foreground colour switch: foreground colour switch: 0 = flash off 0 = bank 0 (colours 0 to 7) 0 = bank 0 (colours 0 to 7) 1 = flash on 1 = bank 1 (colours 8 to 15) 1 = bank 1 (colours 8 to 15) 8 italic switch: background colour duration: background colour duration (set at): 0 = italics off 0 = stop bgc 0 = stop bgc 1 = italics on 1 = set bgc to end of row 1 = set bgc to end of row 9 fringing switch: end of row end of row (set at): 0 = fringing off 0 = continue row 0 = continue row 1 = fringing on 1 = end row: 1 = end row 10 switch for serial coding: switch for serial coding: switch for serial coding: 0 = mode 0 0 = mode 0 0 = mode 0 1 = mode 1 1 = mode 1 1 = mode 1 11 mode bit: mode bit: mode bit: 1 = serial code 1 = serial code 1 = serial code 12 contrast switch: contrast switch: contrast switch: 0 = contrast reduction off 0 = contrast reduction off 0 = contrast reduction off 1 = contrast reduction on 1 = contrast reduction on 1 = contrast reduction on 2000 jun 30 81 philips semiconductors objective speci?cation enhanced tv microcontrollers with on-screen display (osd) saa56xx this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... handbook, full pagewidth gsa089 normal height b 3 b 2 b 1 b 0 b 4 b 5 b 6 b 7 0 1 2 2a 3 3a 4 5 6 6a 7 7a 8 8a 9a 9c column r o w b i t s 0 0 0 0 0 0 0 1 0 1 0 0 0 1 0 1 1 0 0 0 1 0 0 1 a 1 0 1 0 1 1 0 0 0 1 1 0 0 0 1 1 0 0 1 0 0 1 1 1 e 1 1 1 0 double width hold graphics f 1 1 1 1 double size release graphics b 1 0 1 1 start box twist c 1 1 0 0 black back - ground d 1 1 0 1 double height new back - ground a 1 0 1 0 end box separated graphics 9 1 0 0 1 steady contiguous graphics 8 1 0 0 0 flash conceal display 7 0 1 1 1 alpha white graphics white 6 0 1 1 0 alpha cyan graphics cyan 5 0 1 0 1 alpha magenta graphics magenta 4 0 1 0 0 alpha blue graphics blue 3 0 0 1 1 alpha yellow graphics yellow 2 0 0 1 0 alpha green graphics green 0 0 0 0 0 alpha black graphics black 1 0 0 0 1 alpha red graphics red b 1 0 1 1 def 1 1 0 1 1 1 1 0 1 1 1 1 def 1 1 0 1 1 1 1 0 1 1 1 1 double width osd double size osd osd osd osd osd osd osd osd osd osd osd osd osd osd osd osd osd osd osd osd osd osd osd osd osd osd osd osd osd osd osd osd e/w = 0 e/w = 1 osd osd osd osd osd osd osd osd osd osd osd osd osd osd osd osd osd osd osd osd osd osd osd osd osd osd osd osd osd osd osd osd osd nat opt nat opt nat opt nat opt nat opt nat opt nat opt nat opt nat opt nat opt nat opt nat opt nat opt nat opt normal size osd double height osd back- ground white back- ground cyan back- ground magenta back- ground blue back- ground yellow back- ground green back- ground black back ground red osd character dependent on the language of page, refer to national option characters customer definable on-screen display character fig.34 txt basic character set (pan-european). 2000 jun 30 82 philips semiconductors objective speci?cation enhanced tv microcontrollers with on-screen display (osd) saa56xx 23.6 screen and global controls a number of attributes are available that affect the whole display region of a display window, and cannot be applied selectively to regions of the display. 23.6.1 tv scan lines per row the number of tv scan lines per field used for each display row can be defined, the value is independent of the character size being used. the number of lines can be 10, 13 or 16 per display row. the number of tv scan lines per row is defined by txt21.disp lines<1:0>. a value of nine lines per row can be achieved if the display is forced into 525-line display mode by txt17.force disp<1:0>, or if the device is in 10-line mode and the automatic detection circuit within display finds 525-line display syncs. the number of tv lines per row is then set for both the display windows in double window mode. 23.6.2 c haracter matrix (h v) there are three different character matrices available: 12 10, 12 13 and 12 16. the selection is made using txt21.char size<1:0> and is independent of the number of display lines per row. if the character matrix is less than the number of tv scan lines per row, the matrix is padded with blank lines. if the character matrix is greater than the number of tv scan lines, the character is truncated. the character matrix is set for all display windows. 23.6.3 d isplay modes cc: when the superimpose or boxing attribute (see table 32, serial mode 0/1, bit 6) is set, the resulting display depends on the setting of the following screen control mode bits in the mmr display control (see table 33): txt: the display mode is controlled by the bits in the txt5 and txt6 in single window mode or for page a in double window mode, and by the bits in bytes txt24 and txt25 in page b in double window mode. there are three control functions: text on, background on and picture on (see table 34). separate sets of bits are used inside and outside teletext boxes so that different display modes can be invoked. bit(s) txt6 and/or txt25 are used if the newsflash (c5) or subtitle (c6) bits in row 25 of the basic page memory are set; otherwise, byte txt5 and/or txt24 is/are used. this allows the software to set up the type of display required on newsflash and subtitle pages (e.g. text inside boxes, tv picture outside). this will be invoked without any further software intervention when such a page is acquired. when teletext box control characters are present in the display page memory, the appropriate box control bit must be set, txt 2000 jun 30 83 philips semiconductors objective speci?cation enhanced tv microcontrollers with on-screen display (osd) saa56xx table 34 txt display control bits picture on text on background on effect 0 0 x text mode, black screen 0 1 0 text mode, background always black 0 1 1 text mode 1 0 x video mode 1 1 0 mixed text and tv mode 1 1 1 text mode, tv picture outside text area 23.7 screen colour screen colour is displayed from 10.5 to 62.5 ms after the active edge of the hsync input, on tv lines 23 to 310 inclusive for a 625-line display, and on tv lines 17 to 260 inclusive for a 525-line display. cc: the screen colour is defined by the mmr display control and points to a location in the clut table. the screen colour covers the full video width. it is visible when the full text or mixed screen colour mode is set and no foreground or background pixels are being displayed. txt: register bits txt17.screen col<2:0> can be used to define a colour to be displayed instead of tv picture and the black background colour. if the bits are all set to zero, the screen colour is defined as transparent, and tv picture and background colour are displayed as normal. otherwise, the bits define clut entries 9 to 15. in double window mode, txt17.screen col<2:0> applies to text area a and txt27.scrb<2:0> applies to text area b. 23.8 text display controls 23.8.1 t ext display configuration (cc mode ) two types of areas are possible. the one area is static and the other is dynamic. the dynamic area allows scrolling of a region to take place. the areas cannot cross each other. only one scroll region is possible. 23.8.2 d isplay map the display map (see fig.35) allows a flexible allocation of data in the memory to individual rows. sixteen words are provided in the display memory for this purpose. the lower ten bits address the first word in the memory where the row data starts. this value is an offset in terms of 16-bit words from the start of display memory (8000h). the most significant bit enables the display when not within the scroll (dynamic) area (see table 35). the display memory map is fixed at the first 16 words in the closed caption display memory. table 35 display map bit allocation bit function 11 text display enable, valid outside soft scroll area. 0 = disable; 1 = enable. 10 this bit is reserved, should be set to logic 0. 9 to 0 pointer to row data. 2000 jun 30 84 philips semiconductors objective speci?cation enhanced tv microcontrollers with on-screen display (osd) saa56xx mbk966 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 10 11 3 4 9 10 11 12 13 14 15 display possible soft scrolling display possible display possible display map entries display data display memory text area row enable bit = 0 fig.35 display memory map and data pointers. 23.9 soft scroll action the mmr scroll area, mmr scroll range, mmr top scroll line and the mmr status define the dynamic scroll region. the soft scroll area (see fig.36) is enabled when the scon bit is set in mmr status. fig.37 shows the cc text areas and fig.38 shows the txt areas. bits ssp<3:0> define the position of the soft scroll area window and bits ssh<3:0> define the height of the window. both are in mmr scroll range. bits sts<3:0> and bits sps<3:0> define the rows that are scrolled through the window. both are in mmr scroll area. soft scrolling is done by modifying the scroll line value scl<3:0> in mmr top scroll line and the first scroll row value scr<3:0> in the mmr status. if the number of rows allocated to the scroll counter is larger than the defined visible scroll area, parts of rows at the top and bottom may be displayed during the scroll function. the registers can be written throughout the field and the values are updated for display with the next field sync. care should be taken that the register pairs are written to by the software in the same field. only a region that contains only single height rows or only double height rows can be scrolled. txt: the display is organised as a fixed size of 25 rows (0 to 24) of 40 columns (0 to 39), this is the standard size for teletext transmissions. the control data in row 25 is not displayed but is used to configure the display page correctly. 2000 jun 30 85 philips semiconductors objective speci?cation enhanced tv microcontrollers with on-screen display (osd) saa56xx handbook, full pagewidth 15 mbk967 14 13 12 11 10 9 8 7 6 5 soft scroll position pointer ssp < 3:0 > e.g. 6 soft scroll height ssh < 3:0 > e.g. 4 soft scrolling area usable for osd display usable for osd display should not be used for osd display should not be used for osd display start scroll row sts < 3:0 > e.g. 3 start scroll row sps < 3:0 > e.g. 11 4 3 2 1 0 row fig.36 soft scroll area. handbook, full pagewidth mbk977 row 0 row0 row1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 row2 row3 row4 row5 row6 row7 closed captioning data row n closed captioning data row n + 1 closed captioning data row n + 2 closed captioning data row n + 3 closed captioning data row n + 4 row8 row13 visible area for scrolling scroll area offset 0-63 lines row14 p01 nbc fig.37 cc text areas. 2000 jun 30 86 philips semiconductors objective speci?cation enhanced tv microcontrollers with on-screen display (osd) saa56xx handbook, full pagewidth 0 9 023 39 10 mbk968 control data non-displayable data byte 10 reserved row 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 fig.38 txt text area. 2000 jun 30 87 philips semiconductors objective speci?cation enhanced tv microcontrollers with on-screen display (osd) saa56xx 23.10 display positioning 23.10.1 s ingle window mode the display consists of the screen colour covering the whole screen and the text area that is placed within the visible screen area (see fig.39). the screen colour extends over a large vertical and horizontal range so that no offset is needed. the text area is offset in both directions relative to the vertical and horizontal sync pulses. handbook, full pagewidth mgl150 56 m s text area start 0.25 character offset horizontal sync delay horizontal sync vertical sync 6 lines offset text vertical offset screen colour offset = 8 m s text area end screen colour area text area fig.39 display area positioning. 2000 jun 30 88 philips semiconductors objective speci?cation enhanced tv microcontrollers with on-screen display (osd) saa56xx 23.10.2 d ouble window mode the display (see fig.40) consists of the two screen colours covering each half of the screen and two text areas that are placed within the visible screen area. the screen colour extends over a large vertical and horizontal range so that no offset is needed. both text areas are offset in both directions relative to the vertical and horizontal sync pulses. the second page may be positioned relative to hsync delay using the page b position mmr. the visible text area for page a is controlled using the text area start and text area end mmrs. page b visible text area is controlled using the text area start b and text area end b mmrs. handbook, full pagewidth gsa079 horizontal sync vertical sync text vertical offset text area start a text area start b text area end b text area end a screen colour offset = 8 m s 56 m s 6 lines offset text area a text area b screen colour area horizontal sync delay 0.25 character offset 0.25 character offset min. 2 characters spaces page b start fig.40 page positioning. 2000 jun 30 89 philips semiconductors objective speci?cation enhanced tv microcontrollers with on-screen display (osd) saa56xx 23.10.3 s creen colour display area this area is covered by the screen colour, and starts with a fixed offset of 8 m s from the leading edge of the horizontal sync pulse in the horizontal direction. a vertical offset is not necessary. for a summary, see following: horizontal: start at 8 m s after leading edge of h-sync for 56 m s. vertical: line 9, field 1 (321, field 2) to leading edge of vertical sync (line numbering using 625 standard). 23.10.4 t ext display area ( single page ) the text area can be defined to start with an offset in both the horizontal and vertical directions. for a summary, see following: horizontal: up to 48 full sized characters per row. start position setting from 3 to 64 characters relative to hsync delay. fine adjustment in quarter characters. vertical: 256 lines (nominal 41 to 297). start position setting from leading edge of vertical sync legal values are 4 to 64 lines (line numbering using 625 standard). the horizontal offset is set in mmr text area start. the offset is done in full width characters using tas<5:0>, with quarter characters using hop<1:0> for fine setting. values 00h to 03h for tas<5:0> result in a corrupted display. the width of the text area is defined in the text area end register by setting the end character value tae<5:0>. this number determines where the background colour of the text area will end if set to extend to the end of the row. it will also terminate the character fetch process, thus eliminating the necessity of a row end attribute. however, this entails writing to all positions. the vertical offset is set in the text position vertical register. the offset value vol<5:0> is done in number of tv scan lines. note that the text position vertical register should not be set to 00h as the display busy interrupt is not generated in these circumstances. 23.10.5 t ext d isplay a rea (t wo _p age ) control of page a in two page mode is as per the control in single page mode. three extra memory mapped registers control the position of the second page: the text area start b, text area end b and the page b position register. page b positioning register controls the positioning of text area b relative to hsync delay. a minimum two character gap should be allowed between each page to allow the reset of attributes. the vertical offset must be the same for both pages, i.e. range<1:0> and vol<5:0> = rangeb<1:0> and volb<5:0> in text position vertical and vertical range registers (mmr 87f1h, mmr 87e3h and mmr 87e4h). the text area can be defined to start with an offset in the horizontal direction, as follows: up to 48 full sized characters per row. start position setting from 3 to 64 characters relative to value in page b position register. fine adjustment in quarter characters. the horizontal offset is set in the text area start register. the offset is done in full width characters using tas b<5:0>, with quarter characters using hop b<1:0> for fine setting. the width of the text area is defined in the text area end register by setting the end character value tae b<5:0>. this number determines where the background colour of the text area b will end if set to extend to the end of the row. it will also terminate the character fetch process thus eliminating the necessity of a row end attribute. however, this entails writing to all positions. 23.11 character set to facilitate the global nature of the device, the character set can accommodate a large number of characters, which can be stored in different matrices. 23.11.1 c haracter matrices the character matrices that can be accommodated in both display modes are: (h v planes) 12 9 1, 12 10 1, 12 13 1, 12 16 1. these modes allow two colours per character position. in cc mode, two additional character matrices are available to allow four colours per character: (h v planes) 12 13 2, 12 16 2. the characters are stored physically in rom in a 12 10 or 12 16 matrix. 2000 jun 30 90 philips semiconductors objective speci?cation enhanced tv microcontrollers with on-screen display (osd) saa56xx 23.11.2 c haracter set selection four character sets are available in the device. a set can consist of alphanumeric characters, as required by the wst teletext or fcc closed captioning, customer definable osd characters, and special graphic characters. cc: within a closed caption information transmission, only one character set can be used for display. this is selected using the basic set selection txt18.bs<1:0> in single window mode and for page a in double window mode, and txt23.bs b<1:0> for page b in double window mode. when selecting a character set in cc mode, the twist set selection txt19.ts<1:0> should be set to the same value as txt18.bs<1:0> for correct operation. txt: two character sets can be displayed at once. these are the basic g0 set or the alternative g0 set (twist set). the basic set is selected using txt18.bs<1:0> in single window mode or for page a in double window mode, and txt23.bs b<1:0> for page b in double window mode. the alternative character set is defined by txt19.ts<1:0> in single window mode for page a in double window mode, and txt29.ts b<6:5> for page b in double window mode. since the alternative character set is an option, it can be enabled or disabled using txt19.ten for txt19.ts<1:0> and by txt29.ten b for txt29.ts b<6:5>. also, the language code that is defined for the alternative set is defined by txt19.tc<2:0> for txt19.ts<1:0> and by txt30.tc b<7:6> for txt29.ts b<6:5>. the national option table is selected using txt18.not<3:0>. a maximum of 31 national option tables can be defined when combined with the east/ west control bit located in register txt4. in cc osd mode, characters from the four character sets can be displayed on the screen at the same time. this is done using bits 12 to 13 of the parallel code of the character (see table 36). table 36 character set bits coding 23.12 rgb brightness control a brightness control is provided to adjust the rgb upper output voltage level. the nominal value is 1 v into a 150 w resistor, but can be varied between 0.7 and 1.2 v. the brightness is set in the rgb brightness register, see table 37. table 37 rgb brightness 24 memory mapped registers (mmrs) the memory mapped registers are used to control the display as for saa55xx. some additional mmrs are used for saa56xx. see further tables 38 to 40. table 38 mmr address summary bits <13:12> character set 00 set 0 01 set 1 10 set 2 11 set 3 bri3 to bri0 rgb brightness 0000 lowest value ... ... 1111 highest value register number memory address function 0 87f0h display control 1 87f1h text position vertical 2 87f2h text area start 3 87f3h fringing control 4 87f4h text area end 5 87f5h scroll area 6 87f6h scroll range 7 87f7h rgb brightness 8 87f8h status 9 87f9h reserved 10 87fah reserved 11 87fbh reserved 12 87fch hsync delay 13 87fdh vsync delay 14 87feh top scroll line 15 87ffh con?guration 16 87e0h text area start b 17 87e1h text area end b 18 87e2h page b position 19 87e3h text position vertical b 20 87e4h vertical range 2000 jun 30 91 philips semiconductors objective speci?cation enhanced tv microcontrollers with on-screen display (osd) saa56xx this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... table 39 mmr map address r/w name 7 6 5 4 3 2 1 0 reset 87f0h r/w display control src3 src2 src1 src0 - msh mod1 mod0 00h 87f1h r/w text position vertical vpol hpol vol5 vol4 vol3 vol2 vol1 vol0 00h 87f2h r/w text area start hop1 hop0 tas5 tas4 tas3 tas2 tas1 tas0 00h 87f3h r/w fringing control frc3 frc2 frc1 frc0 frdn frde frds frdw 00h 87f4h r/w text area end -- tae5 tae4 tae3 tae2 tae1 tae0 00h 87f5h r/w scroll area ssh3 ssh2 ssh1 ssh0 ssp3 ssp2 ssp1 ssp0 00h 87f6h r/w scroll range sps3 sps2 sps1 sps0 sts3 sts2 sts1 sts0 00h 87f7h r/w rgb brightness vdspol --- bri3 bri2 bri1 bri0 00h 87f8h r status busy field scon flr scr3 scr2 scr1 scr0 00h w -- scon flr scr3 scr2 scr1 scr0 00h 87fch r/w hsync delay - hsd6 hsd5 hsd4 hsd3 hsd3 hsd1 hsd0 00h 87fdh r/w vsync delay - vsd6 vsd5 vsd4 vsd3 vsd2 vsd1 vsd0 00h 87feh r/w top scroll line ---- scl3 scl2 scl1 scl0 00h 87ffh r/w con?guration cc vdel2 vdel1 vdel0 txt/v - 100 hz two_page 00h 87e0h r/w text area start b hopb1 hopb0 tasb5 tasb4 tasb3 tasb2 tasb1 tasb0 00h 87e1h r/w text area end b -- taeb5 taeb4 taeb3 taeb2 taeb1 taeb0 00h 87e2h r/w page b position pgb7 pgb6 pgb5 pgb4 pgb3 pgb2 pgb1 pgb0 00h 87e3h r/w text position vertical b -- volb5 volb4 volb3 volb2 volb1 volb0 00h 87e4h r/w vertical range -- smthb smth range1 range0 rangeb1 rangeb0 00h 2000 jun 30 92 philips semiconductors objective speci?cation enhanced tv microcontrollers with on-screen display (osd) saa56xx table 40 mmr bit de?nition register function display control src3 to src0 screen colour de?nition msh meshing all background colours (logic 1) mod2 to mod0 00 = video 01 = full text 10 = mixed screen colour 11 = mixed video text position vertical vpol inverted input polarity (logic 1) hpol inverted input polarity (logic 1) vol5 to vol0 display start vertical offset from vsync (lines) text area start hop1 to hop0 ?ne horizontal offset in quarter of characters, in single page mode or for page a in double window mode tas5 to tas0 text area start, in single page mode or for page a in double window mode fringing control frc3 to frc0 fringing colour, value address of clut frdn fringe in north direction (logic 1) frde fringe in east direction (logic 1) frds fringe in south direction (logic 1) frdw fringe in west direction (logic 1) text area end tae5 to tae0 text area end, in full characters, in single page mode or for page a in double window mode scroll area ssh3 to ssh0 soft scroll height ssp3 to ssp0 soft scroll position scroll range sps3 to sps0 stop scroll row sts3 to sts0 start scroll row rgb brightness vdspol vds polarity 0 = rgb (1), video (0) 1 = rgb (0), video (1) bri3 to bri0 rgb brightness control 2000 jun 30 93 philips semiconductors objective speci?cation enhanced tv microcontrollers with on-screen display (osd) saa56xx status read busy access to display memory could cause display problems (logic 1) field even ?eld (logic 1) flr active ?ash region background only displayed (logic 1) scr3 to scr0 ?rst scroll row status write scon scroll area enabled (logic 1) flr active ?ash region background colour only displayed (logic 1) scr3 to scr0 ?rst scroll row hsync delay hsd6 to hsd0 hsync delay, in full size characters vsync delay vsd6 to vsd0 vsync delay in number of 8-bit 12 mhz clock cycles top scroll line scl3 to scl0 top line for scroll con?guration cc closed caption mode (logic 1) vdel2 to vdel0 pixel delay between vds and rgb output 000 = vds switched to video, not active 001 = vds active one pixel earlier then rgb 010 = vds synchronous to rgb 100 = vds active one pixel after rgb txt/v busy signal switch; horizontal (logic 1) 100 hz 100 hz mode select; 100hz/120hz timing mode (logic 1) two_page two page mode select; dual page (logic 1) text area start b hop1 to hop0 ?ne horizontal offset in quarter of characters tas5 to tas0 text area start text area end b tae5 to tae0 text area end, in full characters page b position pgb7 to pgb0 page b position text position vertical b volb5 to volb0 page b display start vertical offset from vsync (lines) should equal vol5 to vol0 in double window mode (mmr 87f1h<5:0>) register function 2000 jun 30 94 philips semiconductors objective speci?cation enhanced tv microcontrollers with on-screen display (osd) saa56xx vertical range smthb smoothing on, on page b (logic 1) smth smoothing on, on page a (logic 1) range1 to range0 additional two bits for display vertical offset rangeb1 to rangeb0 additional two bits for display vertical offset on page b register function 25 in-system programming interface a serial programming interface is available for late otp programming. the interface is based on the ieee1149 (jtag) standard, but only two instructions are utilized. table 41 shows which port pins are used for isp. care should be taken during system design to ensure the pins used for serial programming do not cause conflict with the application circuit. it is advised to dedicate the port pins (p2.1, p2.2, p2.3 and p2.4) to isp, and not use them in application. however, if it is necessary to use them in application then they must be assigned as output. the device is placed in isp mode using the reset pin. pin p0.2 must be held high during isp mode. power to the device during isp may be sourced either from the application or from an external source. ground reference between the programmer and the target should be common. table 41 port pins used for isp 26 limiting values in accordance with absolute maximum rating system (iec 60134). note 1. for 5 v tolerant i/os, the maximum value may be 6 v only when v dd is present. pin name function p2.0 en enables jtag operations (speci?c to saa56xx) p2.1 tck test clock p2.2 tms test mode select p2.3 tdi test data in p2.4 tdo test data out vpe vpe 9 v programming voltage reset reset device reset/mode selection alternative: reset reset device reset/mode selection xtalin clk clock 12 mhz symbol parameter conditions min. max. unit v ddx supply voltage (all supplies) - 0.5 +4.0 v v i input voltage (any input) note 1 - 0.5 (v dd + 0.5) or 4.1 v v o output voltage (any output) - 0.5 v dd + 0.5 v i o output current (each output) - 10 ma i iok dc input or output diode current - 20 ma t amb operating ambient temperature - 20 +70 c t stg storage temperature - 55 + 125 c 2000 jun 30 95 philips semiconductors objective speci?cation enhanced tv microcontrollers with on-screen display (osd) saa56xx 27 characteristics v dd = 3.3 v 10%; v ss =0v; t amb = - 20 to +70 c; unless otherwise speci?ed. symbol parameter conditions min. typ. max. unit supplies v ddx any supply voltage (v dd to v ss ) 3.0 3.3 3.6 v i ddp periphery supply current note 1 1 -- ma i ddc core supply current - 15 18 ma i ddc(id) idle mode core supply current - 4.6 6 ma i ddc(pd) power-down mode core supply current - 0.76 1 ma i dda analog supply current - 45 48 ma i dda(id) idle mode analog supply current - 0.87 1 ma i dda(pd) power-down mode analog supply current - 0.45 0.7 ma digital inputs reset v il low-level input voltage -- 1.00 v v ih high-level input voltage 1.85 - 5.5 v v hys hysteresis voltage of schmitt trigger input 0.44 - 0.58 v i li input leakage current v i =0 -- 0.17 m a r pd equivalent pull-down resistance v i =v dd 55.73 70.71 92.45 k w reset, ea, intd v il low-level input voltage -- 0.98 v v ih high-level input voltage 1.73 - 5.5 v v hys hysteresis voltage of schmitt trigger input 0.41 - 0.5 v i li input leakage current v i =v dd -- 0.00 m a r pu equivalent pull-up resistance v i = 0 46.07 55.94 70.01 k w hsync, vsync v il low-level input voltage -- 0.96 v v ih high-level input voltage 1.80 - 5.5 v v hys hysteresis of schmitt trigger input 0.40 - 0.56 v i li input leakage current v i = 0 to v dd -- 0.00 m a 2000 jun 30 96 philips semiconductors objective speci?cation enhanced tv microcontrollers with on-screen display (osd) saa56xx digital outputs frame, vds, rd, wr, psen, ale, a0 to a7, a16, a17, movx_wr, movx_rd, a15_bk, rombk0 to rombk2, rambk0, rambk1 ( push - pull outputs ) v ol low-level output voltage i ol =3ma -- 0.13 v v oh high-level output voltage i oh = 3 ma 2.84 -- v t r output rise time 10% to 90% of v dd , c l =70pf 7.50 8.85 10.90 ns t f output fall time 10% to 90% of v dd , c l =70pf 6.70 7.97 10.00 ns cor ( open - drain output ), a8 to a15 ( push - pull outputs ) v ol low-level output voltage i ol =3ma -- 0.14 v v oh high-level pull-up output voltage i ol = - 3 ma; push-pull 2.84 -- v i li input leakage current v i = 0 to v dd -- 0.12 m a t r output rise time 10% to 90% of v dd , c l =70pf 7.20 8.64 11.10 ns t f output fall time 10% to 90% of v dd , c l =70pf 4.90 7.34 9.40 ns digital input/outputs p0.0 to p0.4, p0.7, p1.0 to p1.1, p2.1 to p2.7, p3.0 to p3.7 v il low-level input voltage -- 0.98 v v ih high-level input voltage 1.78 - 5.50 v v hys hysteresis of schmitt trigger input 0.41 - 0.55 v i li input leakage current v i = 0 to v dd -- 0.01 m a v ol low-level output voltage i ol =4ma -- 0.18 v v oh high-level output voltage i oh = - 4 ma push-pull 2.81 -- v t r output rise time 10% to 90% of v dd , c l = 70 pf push-pull 6.50 8.47 10.70 ns t f output fall time 10% to 90% of v dd , c l =70pf 5.70 7.56 10.00 ns p1.2, p1.3 and p2.0 v il low-level input voltage -- 0.99 v v ih high-level input voltage 1.80 - 5.50 v v hys hysteresis voltage of schmitt trigger input 0.42 - 0.56 v i li input leakage current v i = 0 to v dd -- 0.02 m a v ol low-level output voltage i ol =4ma -- 0.17 v v oh high-level output voltage i oh = - 4 ma push-pull 2.81 -- v t r output rise time 10% to 90% of v dd ; c l = 70 pf push-pull 7.00 8.47 10.50 ns t f output fall time 10% to 90% of v dd ; c l =70pf 5.40 7.36 9.30 ns symbol parameter conditions min. typ. max. unit 2000 jun 30 97 philips semiconductors objective speci?cation enhanced tv microcontrollers with on-screen display (osd) saa56xx p0.5 and p0.6 v il low-level input voltage -- 0.98 v v ih high-level input voltage 1.82 - 5.50 v i li input leakage current v i = 0 to v dd -- 0.11 m a v hys hysteresis voltage of schmitt trigger input 0.42 - 0.58 v v ol low-level output voltage i ol =8ma -- 0.20 v v oh high-level output voltage i oh = - 8 ma push-pull 2.76 -- v t r output rise time 10% to 90% of v dd ; c l = 70 pf push-pull 7.40 8.22 8.80 ns t f output fall time 10% to 90% of v dd ; c l =70pf 4.20 4.57 5.20 ns p1.4 to p1.7 ( open - drain ) v il low-level input voltage -- 1.08 v v ih high-level input voltage 1.99 - 5.50 v v hys hysteresis voltage of schmitt trigger input 0.49 - 0.60 v i li input leakage current v i = 0 to v dd -- 0.13 m a v ol low-level output voltage i ol =8ma -- 0.35 v t f output fall time 10% to 90% of v dd ; c l =70pf 69.70 83.67 103.30 ns t f(i2c) output fall time in relation to the i 2 c-bus speci?cations 3 v to 1.5 v at i ol =3ma c l = 400 nf - 57.80 - ns ad0 to ad7 ( quasi - bidirectional ) v il low-level input voltage -- 0.98 v v ih high-level input voltage 1.82 - 5.50 v v hys hysteresis voltage of schmitt trigger input 0.40 - 0.58 v i li input leakage current v i =0,v dd /2, v dd -- 0.12 m a v ol low-level output voltage i ol =3ma -- 0.14 v v oh high-level output voltage i ol = - 3 ma; push-pull 2.84 -- v t r output rise time 10% to 90% of v dd ; c l =70pf 7.20 8.64 11.10 ns t f output fall time 10% to 90% of v dd ; c l =70pf 4.90 7.34 9.40 ns symbol parameter conditions min. typ. max. unit 2000 jun 30 98 philips semiconductors objective speci?cation enhanced tv microcontrollers with on-screen display (osd) saa56xx analog inputs cvbs0 and cvbs1 v sync sync voltage amplitude 0.1 0.3 0.6 v v vid(p-p) video input voltage amplitude (peak-to-peak value) 0.7 1.0 1.4 v z source source impedance 0 - 250 w v ih high-level input voltage 3.0 - v dda + 0.3 v c i input capacitance -- 10 pf iref r gnd resistor to ground resistor tolerance 2% - 24 - k w adc0 to adc3 v ih high-level input voltage -- v dda v c i input capacitance -- 10 pf vpe v ih high-level input voltage -- 9.0 v analog outputs r, g and b i ol output current (black level) v dda = 3.3 v - 10 - +10 m a i oh output current (maximum intensity) v dda = 3.3 v intensity level code = 31 dec 6.0 6.67 7.3 ma output current (70% of full intensity) v dda = 3.3 v intensity level code = 0 dec 4.2 4.7 5.1 ma r load load resistor to v ssa resistor tolerance 5% - 150 -w c l load capacitance -- 15 pf t r output rise time 10% to 90% full intensity - 16.1 - ns t f output fall time 10% to 90% full intensity - 14.5 - ns analog input/output sync_filter c sync storage capacitor to ground - 100 - nf v sync sync ?lter level voltage for nominal sync amplitude 0.35 0.55 0.75 v crystal oscillator xtalin v il low-level input voltage v ssa -- v v ih high-level input voltage -- v dda v c i input capacitance -- 10 pf xtalout c o output capacitance -- 10 pf symbol parameter conditions min. typ. max. unit 2000 jun 30 99 philips semiconductors objective speci?cation enhanced tv microcontrollers with on-screen display (osd) saa56xx note 1. peripheral current is dependent on external components and voltage levels on i/os. 2. crystal order number 4322 143 05561. 3. if the 4322 143 05561 crystal is not used, then the formulae in the crystal specification should be used. where c io = 7 pf, the mean of the capacitances due to the chip at xtalin and at xtalout. c ext is a value for the mean of the stray capacitances due to the external circuit at xtalin and xtalout. the maximum value for the crystal holder capacitance is to ensure startup, c osc may need to be reduced from the initially selected value. 4. c osc(typ) =2c l - c io - c ext 5. c 0(max) =35 - 1 2 (c osc +c io +c ext ) crystal speci?cation; notes 2 and 3 f xtal nominal frequency fundamental mode - 12 - mhz c l crystal load capacitance - -30 pf c 1 crystal motional capacitance t amb =25 c -- 20 ff r r resonance resistance t amb =25 c -- 60 w c osc capacitors at xtalin, xtalout t amb =25 c - note 4 - pf c 0 crystal holder capacitance t amb =25 c -- note 5 pf t xtal temperature range - 20 +25 +85 c x j adjustment tolerance t amb =25 c -- 50 10 - 6 x d drift -- 100 10 - 6 symbol parameter conditions min. typ. max. unit 2000 jun 30 100 philips semiconductors objective speci?cation enhanced tv microcontrollers with on-screen display (osd) saa56xx 28 quality and reliability this device will meet philips semiconductors general quality specification for integrated circuits snw-fq-611d . the principal requirements are shown in tables 42 to 44. 28.1 lot acceptance table 42 acceptance tests per lot note 1. ppm = fraction of defective devices, in parts per million. 28.2 reliability performance table 43 reliability tests (by process family) note 1. fpm = fraction of devices failing at test condition, in failures per million. table 44 reliability tests (by device type) test requirements (1) mechanical cumulative target: <80 ppm electrical cumulative target: <100 ppm test conditions requirements (1) high temperature operating life 168 hours at t j = 150 c <500 fpm humidity life temperature, humidity, bias 1000 hours, 85 c, 85% rh (or equivalent test) <1000 fpm temperature cycling performance 65 c to 150 c <2000 fpm test conditions requirements esd and latch-up esd human body model 100 pf, 1.5 k w 2000 v esd machine model 200 pf, 0 w 200 v latch-up 100 ma, 1.5 v dd(max) 2000 jun 30 101 philips semiconductors objective speci?cation enhanced tv microcontrollers with on-screen display (osd) saa56xx this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... 29 application information 29.1 application diagram full pagewidth gsa080 93 v dd v dd v afc av status program + program - plus( + ) minus( - ) menu v tune v ss v ss v ss v dd v dd v dd v dd v ssc v ddp v ddc v ssp v ssa v ss vpe v ss v ss v ss p2.1/pwm0 94 p2.2/pwm1 95 p2.3/pwm2 96 p2.4/pwm3 97 p2.5/pwm4 98 p2.6/pwm5 1 p2.7/pwm6 2 p3.0/adc0 p3.1/adc1 p3.2/adc2 p0.0/rx vhf-l vhf-h uhf tv control signals p3.3/adc3 4 5 6 11 16 17 18 22 24 13 28 29 p0.1/tx p0.2/int2 p0.3/int3 p0.4/int4 p0.5 p0.6 p0.7/t2 g b v dda hsync vds r vsync xtalout xtalin oscgnd p1.0/int1 reset p3.4/pwm7/t2ex iref 100 nf 100 nf 100 nf frame sync_filter cvbs1 cvbs0 cvbs (if) cvbs (scart) 30 31 32 35 34 43 41 21, 42 100 83 82 81 80 79 78 76 75 73 71 70 69 63 12, 60 55 53 52 48 47 46 45 44 84 p2.0/tpwm a2 p1.4/scl1 p1.7/sda0 p1.6/scl0 p1.3/t1 p1.2/int0 p1.1/t0 p1.5/sda1 sda a1 scl a0 rc brightness contrast saturation hue volume (l) volume (r) v dd v ss 1 k w 1 k w 150 w 24 k w v dd 40 v v ss v ss v dd v ss ph2369 47 m f v dd v ss v dd 100 nf cor v ss v dd 47 m f 10 m f 100 nf 56 pf v dd v dd v dd v ss v ss eeprom pcf8582e saa56xx (sot407-1) ir receiver 12 mhz to tv's display circuits tv control signals field flyback line flyback ea 14 v dd reset 72 v dd fig.41 application diagram. bi-directional ports have been configured as open-drain, output ports have been configured as push-pull. 2000 jun 30 102 philips semiconductors objective speci?cation enhanced tv microcontrollers with on-screen display (osd) saa56xx 29.2 external sram implementation 29.2.1 a pplication d iagram gsa081 handbook, full pagewidth sram saa56xx ad0 ad1 ad2 ad3 ad4 ad5 ad6 ad7 a0 rambk1 a1 a2 a3 a12 a13 a5 a4 a15_bk d7 1 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 75 74 73 72 71 70 69 68 67 66 a11 rambk0 a10 a9 a8 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 26 d6 d5 d4 d3 d2 d1 d0 a7 a7 a6 a6 a5 a4 a3 a2 a1 a0 a17 a16 a15 a14 a13 a12 a11 a10 a9 a8 wr rd/wr rd a14 oe fig.42 application diagram for multipage. 2000 jun 30 103 philips semiconductors objective speci?cation enhanced tv microcontrollers with on-screen display (osd) saa56xx 29.2.2 a pplication notes ports ad0 to ad7 of the microcontroller can be connected to pins d0 to d7 of the sram in any order. for the addressing, the lower group of address lines (a0 to a8) and the upper group of address lines (a9 to a14, a15_bk, rambk0 and rambk1) may be connected in any order within the groups, provided that the full 256 kbytes of external sram is used. fig.42 shows the application diagram for multipage. when using an external sram smaller than 256 kbytes, the relevant number of bits from the microcontroller address bus should be disconnected, always removing the most significant bits first. for power saving modes, it might be advisable to control the ce pin of the sram module(s) using one of the microcontroller ports to de-select the sram. 29.2.3 e xternal data memory access table 45 external data memory access see figs. 43 and 44. note 1. the external sram is intended to be used with the multipage software, therefore only the 12 mhz clock microcontroller timings are provided. 29.2.3.1 symbol explanations each timing symbol has five characters. the first character is always t (time). depending on their positions, the other characters indicate the name of a signal or the logical status of that signal. the designations are: a = address c = clock d = input data h = logic level high i = instruction (program memory contents) l = logic level low, or ale p = psen q = output data r = rd signal t = time v = valid w = wr signal x = no longer a valid logic level z = float examples: t avll = time for address valid to ale low. t llpl = time for ale to psen low. symbol parameter typical (1) unit t rlrh rd pulse width 250 ns t wlwh wr pulse width 250 ns t rldv rd low to valid data in 198 ns t rhdx data hold after rd 0 ns t rhdz data ?oat after rd tbd ns t llwl ale low to rd or wr low 132 ns t avwl address valid to wr low or rd low 172 ns t qvwx data valid to wr low 89 ns t whqx data hold after wr 15 ns t rlaz rd low to address ?oat tbd ns t whlh rd or wr high to ale high 40 ns 2000 jun 30 104 philips semiconductors objective speci?cation enhanced tv microcontrollers with on-screen display (osd) saa56xx handbook, full pagewidth gsa082 t llwl t rlrh ale psen rd ad < 0 : 7 > a < 0 : 14 > , a15_bk, rambk < 0 : 1 > a0-a7 data in a0-a7 instr in t avwl t avll t rhdx t llax t rlaz t rldv t rhdz t whlh fig.43 external data memory read cycle. handbook, full pagewidth gsa083 t llwl t wlwh ale psen wr ad < 0 : 7 > a < 0 : 14 > , a15_bk, rambk < 0 : 1 > a0-a7 data out a0-a7 from pcl instr in t avwl t avll t llax t qvwx t whqx t whlh fig.44 external data memory write cycle. 2000 jun 30 105 philips semiconductors objective speci?cation enhanced tv microcontrollers with on-screen display (osd) saa56xx 30 emc guidelines optimization of circuit return paths and minimisation of common mode emission will be assisted by using a double sided printed-circuit board with low inductance ground plane. on a single sided printed-circuit board, a local ground plane under the whole ic should be present, as shown in fig.45. this should be connected by the widest possible connection back to the pcb ground connection, and bulk electrolytic decoupling capacitor. it should preferably not connect to other grounds on the way and no wire links should be present in this connection. the use of wire links increases ground bounce by introducing inductance into the ground. the supply pins can be decoupled at the pin to the ground plane under the ic. this is easily accomplished using surface mount capacitors, which are more effective than leaded components at high frequency. using a device socket will unfortunately add to the area and inductance of the external bypass loop. a ferrite bead or inductor with resistive characteristics at high frequencies may be utilised in the supply line close to the decoupling capacitor to provide a high impedance. to prevent pollution by conduction onto the signal lines (which may then radiate), signals connected to the v dd supply via a pull-up resistor should not be connected to the ic side of this ferrite component. pin oscgnd should be connected only to the crystal load capacitors and not the local or circuit gnd. physical connection distances to associated active devices should be short. output traces should be routed with close proximity mutually coupled ground return paths. handbook, full pagewidth electrolytic decoupling capacitor (2 m f) ferrite beads sm decoupling capacitors (10 to 100 nf) under-ic gnd plane ic mbk979 v ssc v ssa v ddp v ssp v ddc v dda gnd + 3.3 v other gnd connections under-ic gnd plane gnd connection note: no wire links fig.45 power supply connections for emc. 2000 jun 30 106 philips semiconductors objective speci?cation enhanced tv microcontrollers with on-screen display (osd) saa56xx 31 package outline unit a max. a 1 a 2 a 3 b p ce (1) eh e ll p z y w v q references outline version european projection issue date iec jedec eiaj mm 1.6 0.15 0.05 1.45 1.35 0.25 0.27 0.17 0.20 0.09 14.1 13.9 0.5 16.25 15.75 1.15 0.85 7 0 o o 0.08 0.08 0.2 1.0 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. 0.75 0.45 sot407-1 136e20 ms-026 00-01-19 00-02-01 d (1) (1) (1) 14.1 13.9 h d 16.25 15.75 e z 1.15 0.85 d b p e q e a 1 a l p detail x l (a ) 3 b 25 c d h b p e h a 2 v m b d z d a z e e v m a x 1 100 76 75 51 50 26 y pin 1 index w m w m 0 5 10 mm scale lqfp100: plastic low profile quad flat package; 100 leads; body 14 x 14 x 1.4 mm sot407-1 2000 jun 30 107 philips semiconductors objective speci?cation enhanced tv microcontrollers with on-screen display (osd) saa56xx 32 soldering 32.1 introduction to soldering surface mount packages this text gives a very brief insight to a complex technology. a more in-depth account of soldering ics can be found in our data handbook ic26; integrated circuit packages (document order number 9398 652 90011). there is no soldering method that is ideal for all surface mount ic packages. wave soldering is not always suitable for surface mount ics, or for printed-circuit boards with high population densities. in these situations reflow soldering is often used. 32.2 re?ow soldering reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. several methods exist for reflowing; for example, infrared/convection heating in a conveyor type oven. throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. typical reflow peak temperatures range from 215 to 250 c. the top-surface temperature of the packages should preferable be kept below 230 c. 32.3 wave soldering conventional single wave soldering is not recommended for surface mount devices (smds) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. to overcome these problems the double-wave soldering method was specifically developed. if wave soldering is used the following conditions must be observed for optimal results: use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. for packages with leads on two sides and a pitch (e): C larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; C smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves at the downstream end. for packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves downstream and at the side corners. during placement and before soldering, the package must be fixed with a droplet of adhesive. the adhesive can be applied by screen printing, pin transfer or syringe dispensing. the package can be soldered after the adhesive is cured. typical dwell time is 4 seconds at 250 c. a mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 32.4 manual soldering fix the component by first soldering two diagonally-opposite end leads. use a low voltage (24 v or less) soldering iron applied to the flat part of the lead. contact time must be limited to 10 seconds at up to 300 c. when using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 c. 2000 jun 30 108 philips semiconductors objective speci?cation enhanced tv microcontrollers with on-screen display (osd) saa56xx 32.5 suitability of surface mount ic packages for wave and re?ow soldering methods notes 1. all surface mount (smd) packages are moisture sensitive. depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). for details, refer to the drypack information in the data handbook ic26; integrated circuit packages; section: packing methods . 2. these packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version). 3. if wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. the package footprint must incorporate solder thieves downstream and at the side corners. 4. wave soldering is only suitable for lqfp, tqfp and qfp packages with a pitch (e) equal to or larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 5. wave soldering is only suitable for ssop and tssop packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. package soldering method wave reflow (1) bga, lfbga, sqfp, tfbga not suitable suitable hbcc, hlqfp, hsqfp, hsop, htqfp, htssop, sms not suitable (2) suitable plcc (3) , so, soj suitable suitable lqfp, qfp, tqfp not recommended (3)(4) suitable ssop, tssop, vso not recommended (5) suitable 2000 jun 30 109 philips semiconductors objective speci?cation enhanced tv microcontrollers with on-screen display (osd) saa56xx 33 data sheet status note 1. please consult the most recently issued data sheet before initiating or completing a design. data sheet status product status definitions (1) objective speci?cation development this data sheet contains the design target or goal speci?cations for product development. speci?cation may change in any manner without notice. preliminary speci?cation quali?cation this data sheet contains preliminary data, and supplementary data will be published at a later date. philips semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. product speci?cation production this data sheet contains ?nal speci?cations. philips semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. 34 definitions short-form specification ? the data in a short-form specification is extracted from a full data sheet with the same type number and title. for detailed information see the relevant data sheet or data handbook. limiting values definition ? limiting values given are in accordance with the absolute maximum rating system (iec 60134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the specification is not implied. exposure to limiting values for extended periods may affect device reliability. application information ? applications that are described herein for any of these products are for illustrative purposes only. philips semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 35 disclaimers life support applications ? these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips semiconductors for any damages resulting from such application. right to make changes ? philips semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. philips semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. 36 purchase of philips i 2 c components purchase of philips i 2 c components conveys a license under the philips i 2 c patent to use the components in the i 2 c system provided the system conforms to the i 2 c specification defined by philips. this specification can be ordered using the code 9398 393 40011. 2000 jun 30 110 philips semiconductors objective speci?cation enhanced tv microcontrollers with on-screen display (osd) saa56xx notes 2000 jun 30 111 philips semiconductors objective speci?cation enhanced tv microcontrollers with on-screen display (osd) saa56xx notes ? philips electronics n.v. sca all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owne r. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not con vey nor imply any license under patent- or other industrial or intellectual property rights. internet: http://www.semiconductors.philips.com 2000 70 philips semiconductors C a worldwide company for all other countries apply to: philips semiconductors, marketing communications, building be-p, p.o. box 218, 5600 md eindhoven, the netherlands, fax. +31 40 27 24825 argentina: see south america australia: 3 figtree drive, homebush, nsw 2140, tel. +61 2 9704 8141, fax. +61 2 9704 8139 austria: computerstr. 6, a-1101 wien, p.o. box 213, tel. +43 1 60 101 1248, fax. +43 1 60 101 1210 belarus: hotel minsk business center, bld. 3, r. 1211, volodarski str. 6, 220050 minsk, tel. +375 172 20 0733, fax. +375 172 20 0773 belgium: see the netherlands brazil: see south america bulgaria: philips bulgaria ltd., energoproject, 15th floor, 51 james bourchier blvd., 1407 sofia, tel. +359 2 68 9211, fax. +359 2 68 9102 canada: philips semiconductors/components, tel. +1 800 234 7381, fax. +1 800 943 0087 china/hong kong: 501 hong kong industrial technology centre, 72 tat chee avenue, kowloon tong, hong kong, tel. +852 2319 7888, fax. +852 2319 7700 colombia: see south america czech republic: see austria denmark: sydhavnsgade 23, 1780 copenhagen v, tel. +45 33 29 3333, fax. +45 33 29 3905 finland: sinikalliontie 3, fin-02630 espoo, tel. +358 9 615 800, fax. +358 9 6158 0920 france: 51 rue carnot, bp317, 92156 suresnes cedex, tel. +33 1 4099 6161, fax. +33 1 4099 6427 germany: hammerbrookstra?e 69, d-20097 hamburg, tel. +49 40 2353 60, fax. +49 40 2353 6300 hungary: see austria india: philips india ltd, band box building, 2nd floor, 254-d, dr. annie besant road, worli, mumbai 400 025, tel. +91 22 493 8541, fax. +91 22 493 0966 indonesia: pt philips development corporation, semiconductors division, gedung philips, jl. buncit raya kav.99-100, jakarta 12510, tel. +62 21 794 0040 ext. 2501, fax. +62 21 794 0080 ireland: newstead, clonskeagh, dublin 14, tel. +353 1 7640 000, fax. +353 1 7640 200 israel: rapac electronics, 7 kehilat saloniki st, po box 18053, tel aviv 61180, tel. +972 3 645 0444, fax. +972 3 649 1007 italy: philips semiconductors, via casati, 23 - 20052 monza (mi), tel. +39 039 203 6838, fax +39 039 203 6800 japan: philips bldg 13-37, kohnan 2-chome, minato-ku, tokyo 108-8507, tel. +81 3 3740 5130, fax. +81 3 3740 5057 korea: philips house, 260-199 itaewon-dong, yongsan-ku, seoul, tel. +82 2 709 1412, fax. +82 2 709 1415 malaysia: no. 76 jalan universiti, 46200 petaling jaya, selangor, tel. +60 3 750 5214, fax. +60 3 757 4880 mexico: 5900 gateway east, suite 200, el paso, texas 79905, tel. +9-5 800 234 7381, fax +9-5 800 943 0087 middle east: see italy netherlands: postbus 90050, 5600 pb eindhoven, bldg. vb, tel. +31 40 27 82785, fax. +31 40 27 88399 new zealand: 2 wagener place, c.p.o. box 1041, auckland, tel. +64 9 849 4160, fax. +64 9 849 7811 norway: box 1, manglerud 0612, oslo, tel. +47 22 74 8000, fax. +47 22 74 8341 pakistan: see singapore philippines: philips semiconductors philippines inc., 106 valero st. salcedo village, p.o. box 2108 mcc, makati, metro manila, tel. +63 2 816 6380, fax. +63 2 817 3474 poland : al.jerozolimskie 195 b, 02-222 warsaw, tel. +48 22 5710 000, fax. +48 22 5710 001 portugal: see spain romania: see italy russia: philips russia, ul. usatcheva 35a, 119048 moscow, tel. +7 095 755 6918, fax. +7 095 755 6919 singapore: lorong 1, toa payoh, singapore 319762, tel. +65 350 2538, fax. +65 251 6500 slovakia: see austria slovenia: see italy south africa: s.a. philips pty ltd., 195-215 main road martindale, 2092 johannesburg, p.o. box 58088 newville 2114, tel. +27 11 471 5401, fax. +27 11 471 5398 south america: al. vicente pinzon, 173, 6th floor, 04547-130 s?o paulo, sp, brazil, tel. +55 11 821 2333, fax. +55 11 821 2382 spain: balmes 22, 08007 barcelona, tel. +34 93 301 6312, fax. +34 93 301 4107 sweden: kottbygatan 7, akalla, s-16485 stockholm, tel. +46 8 5985 2000, fax. +46 8 5985 2745 switzerland: allmendstrasse 140, ch-8027 zrich, tel. +41 1 488 2741 fax. +41 1 488 3263 taiwan: philips semiconductors, 5f, no. 96, chien kuo n. rd., sec. 1, taipei, taiwan tel. +886 2 2134 2451, fax. +886 2 2134 2874 thailand: philips electronics (thailand) ltd., 60/14 moo 11, bangna trad road km. 3, bagna, bangkok 10260, tel. +66 2 361 7910, fax. +66 2 398 3447 turkey: yukari dudullu, org. san. blg., 2.cad. nr. 28 81260 umraniye, istanbul, tel. +90 216 522 1500, fax. +90 216 522 1813 ukraine : philips ukraine, 4 patrice lumumba str., building b, floor 7, 252042 kiev, tel. +380 44 264 2776, fax. +380 44 268 0461 united kingdom: philips semiconductors ltd., 276 bath road, hayes, middlesex ub3 5bx, tel. +44 208 730 5000, fax. +44 208 754 8421 united states: 811 east arques avenue, sunnyvale, ca 94088-3409, tel. +1 800 234 7381, fax. +1 800 943 0087 uruguay: see south america vietnam: see singapore yugoslavia: philips, trg n. pasica 5/v, 11000 beograd, tel. +381 11 3341 299, fax.+381 11 3342 553 printed in the netherlands 753504/01/pp 112 date of release: 2000 jun 30 document order number: 9397 750 06662 |
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